Hi all!
I have a design with combinational clocks. The synthesis report asks me to use CLOCK_SIGNAL with these signals. However, I have a problem using this constraint. It can only be used through Verilog/VHDL and not from constraints editor(Xilinx ISE 5.1). So i am using the following statement:
//synthesis attribute CLOCK_SIGNAL of J1106 is yes;
However, this doesn't seem to work. Their is still the message in synthesis report "Please use CLOCK_SIGNAL constraint....". The hierarchy of my design is as follows:
module DFF_54174.v instantiated in module SHEET3.v as Z158. Module SHEET3.v instantiated in module DMAB.v [TOP LEVEL] as CIRCUIT3. The signal to which i want to apply constraint is pin10 of DFF_54174 tied to J1106 in SHEET3.v. J1106 is a wire in TOP level DMAB.v.
Now is my above constraint statement OK? If yes why is now working? Where to place this statement? TOP level? or in SHEET3.V or in DFF_54174.v ? The synthesis report indicates this signal as : CIRCUIT3_J11061:O ? should i use this instead of J1106? Should i use quotes around [yes]?
Regards Rider