How to bound a Cores generated output in Modelsim

Sep 06, 2006 7 Replies
F

Hi, I am learning Xilinx ISE Webpack 8.2. There is an example watchvhd.ise in the package. The component tenths is generated from Cores utility. When I go to Modelsim to do behavioral simulation. It says:



# -- Compiling entity testbench # -- Compiling architecture testbench_arch of testbench # vsim -lib work -t 1ps testbench # Loading C:\Modeltech_xe_starter\win32xoem/../std.standard # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading work.testbench(testbench_arch) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.stopwatch(inside) # Loading work.statmach(behavior) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading work.dcm1(behavioral) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.ibufg(ibufg_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.bufg(bufg_v) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.vital_primitives(body) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vpkg(body) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.dcm(dcm_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.dcm_clock_divide_by_2(dcm_clock_divide_by_2_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.dcm_maximum_period_check(dcm_maximum_period_check_v) # Loading C:\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.dcm_clock_lost(dcm_clock_lost_v) # ** Warning: (vsim-3473) Component instance "xcounter : tenths" is not bound. # Time: 0 ps Iteration: 0 Region: /testbench/uut File: stopwatch.vhd # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.decode(behavioral) # Loading work.cnt60(inside) # Loading C:\Modeltech_xe_starter\win32xoem/../synopsys.attributes # Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_misc(body) # Loading work.smallcntr(inside) # Loading work.hex2led(behavioral) # .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf # .main_pane.workspace # .main_pane.signals.interior.cs



I have browsed the group. tenths.vho file is in the directory. How modelsim to bound it in simulation? Thanks you.



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A

This indicates to me that "xcounter : tenths" is not present. Does it exit in your "work" directory? Has it been compiled correctly, without an error ?

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F

No. It is not in the work directory. How and where (In modelsim?) to compile the .vho file?

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A

Yuu must compile it, just like any other hdl file.

Assuming you have a simulation wrapper for your design containing all IO parts of the FPGA which are not physically present, you just copy this wrapper into a new file and replace the complete design by the vho.

Did you allready succed in compling and simulating the complete design, or parts of the design?

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F

In ISE, I can see tenths.xco file at the source tab. I can see tenths.vhd and tenths.xco at the library tab. Although I cannot go on the behavioral simulation, it can go with the post-translate simulation. I don't know why the behavioral simulation cannot do. Thank you.

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F

This top file includes the component description of tenths. Is it enough?

library IEEE; use IEEE.std_logic_1164.all;

--synopsys translate_off library UNISIM; use unisim.vcomponents.all;

--synopsys translate_on

entity stopwatch is port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; STRTSTOP : in STD_LOGIC; TENTHSOUT : out STD_LOGIC_VECTOR(9 downto 0); ONESOUT : out STD_LOGIC_VECTOR(6 downto 0); TENSOUT : out STD_LOGIC_VECTOR(6 downto 0)); end stopwatch;

architecture inside of stopwatch is

component statmach port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; STRTSTOP : in STD_LOGIC; locked : std_logic; CLKEN : out STD_LOGIC; RST : out STD_LOGIC); end component;

COMPONENT testip PORT( RST_IN : IN std_logic; CLKIN_IN : IN std_logic; LOCKED_OUT : OUT std_logic; CLK0_OUT : OUT std_logic; CLKIN_IBUFG_OUT : OUT std_logic ); END COMPONENT;

component tenths port ( Q: OUT std_logic_VECTOR(3 downto 0); CLK: IN std_logic; Q_THRESH0: OUT std_logic; CE: IN std_logic; AINIT: IN std_logic); end component;

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A

Well, I think this is your simulation bench (or the working toplevel, no matter).

To work properly, Modelsim needs all the mentioned vhdl-files. Typically you will create a project, add all the required files, and do a recompile on the particular file, once you edited it.

Perhaps you choose "compile" manually in Modelsim and click on the tenth.hdl. Maybe it does not compile due to an error ...

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B

You need to compile tenths.vhd (in ModelSim) into the appropriate library (e.g. Work, unless there is an embedded configuration for Tenths in your top level design; like "For all: tenths Use mylib.tenths.myarch;" In which case, compile it into "mylib")

If this still doesn't bind the component, check that the "tenths" entity in tenths.vhd matches the component declaration in your top level design. Modelsim will look for an entity with the same interface as your component declaration, e.g. number and names and types of ports. If there are any differences, it won't find a match. So fix the component declaration - or the entity, as appropriate.

- Brian

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