Hi everyone, I am fairly new to VHDL and had several questions about types conversions that I've numbered for easiness of separating them. Any help would be greatly appreciated.
I am using signed type throughout my program. Now, there is one third party function that outputs std_logic_vector, that I have to use. The function looks like its std_logic_vector signal is in signed format (the sine wave with positive and negative values). 1. Can I just assume that it's in 2's compliment format similar to signed? In other words, how does STD_LOGIC_VECTOR holds signed numbers?
- I understand that if I would like to match it to my internal signals, I would have to cast that signal to SIGNED. So, can I do SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of the above statement? Would it take the signal inside and convert it to 2's comliment? That would be useless for me if the signal is already in 2's compliment. If that's not correct, please let me know how can go around this.
- I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just magnitude) as long as you keep in mind in which context you are using it. However, the moment you start using SIGNED function, how does VHDL compiler recognize the numbers from then? Does it still treat them as STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's compliement?
- I've read that ieee.std_logic_arith and ieee.numeric_std are mutually exclusive libraries that you cannot use at the same time. Maybe using one or another one would somehow answer my questions above..
Big thanks in advance! Kofeyok