Writing output signals to text file (VHDL)?

The writing is working now (I shrinked the input file too much, so there was nothing to be processed. Still have question about converting two's complement to integer.

Vitaliy Vitaliy wrote:

To convert a std_logic_vector (ex. My_slv) that is being interpreted as 'twos complement' to an integer use...

to_integer(signed(My_slv))

KJ

I'm getting this error in ModelSim:

# ** Error: design_t> > The writing is working now (I shrinked the input file too much, so

In to_integer(signed(My_slv)), does signed relate to integer or to arithmetic (I think integer, but just checking)? Because there are two libraries:

ieee.numeric_std.signed and ieee.std_logic_arith.signed

So, when I specify the complete name of the library (i.e ieee.numeric_std.signed), the compiler is happy.

Vitaliy

KJ wrote:

Don't use both numeric_std and std_logic_arith. They have different definitions for the same function names. If you do use both, then you have to specify which one each library call belongs to.

'signed' relates to how the std_logic_vector is supposed to be interpreted. All by itself std_logic_vectors have no implicit 'sign' bit or any sort of numerical interpretation so, for example, "10000000" could mean either 128 (decimal) or a negative number or just a collection of 8 bits of 'stuff'. signed("10000000") means that the bit on the left is to be interpreted as a sign bit and the vector is a twos complement representation of a number, which means that in this case we're talking about a negative number, 8 bit numbers can represent anything from -128 to +127.

There is also the function unsigned() which says that there is no sign bit in the std_logic_vector argument so unsigned("10000000") is a positive number, in this case 128. If you're only dealing with things that cannot be negative there is no value in the 'sign' bit, 8 bit numbers can represent anything from 0 to 255.

To convert the std_logic_vector to an integer via the to_integer() function you need to supply it with an argument that has a specific interpretation which is what the signed() and unsigned() functions provide.

Don't use std_logic_arith, it has problems and it is not a standard.

Since both libraries have a 'signed' function and the compiler can't tell the difference between the two of them by their usage, specifying the full path name to the function that you want is the work around. Sometimes this is handy but in this particular instance you'd be better off getting rid of std_logic_arith.

By the way, since the title of the thread is ''Writing output signals to text file (VHDL)" I'm guessing that you actually want to write out this integer as text in which case you'll probably be needing to convert that integer to a text string in order to write it to a text file. This can be done with integer'image(My_integer) or combining with the conversion of the std_logic_vector to an integer.... integer'image(to_integer(signed(My_slv))

KJ

Thanks,

I realized from the error that each library has signed function and that confuses the compiler, but didn't know std_logic_arith is not a standard and I have to use numeric_std. When would one want to use std_logic_arith library over numeric_std?

integer'image returns the textual representation of "int", but what is wrong with simply writing "int"? Or I guess I should ask what the difference between two is? (Is output of "int" type integer and output of "integer'image" type char (or is it string of integers?)?)

Vitaliy

KJ wrote:

'Never' would be the short answer to when you should use std_logic_arith when writing new code.

If instead you're maintaining and supporting existing code that somebody else wrote and they used std_logic_arith then in order to try to avoid introducing new bugs caused by subtle differences between the two libraries you might want to continue to have this legacy code use std_logic_arith if you're making only otherwise minor changes.

I'm not sure what exactly you mean here or exactly what file format you're really trying to write. Try having the simulation write out the file and see what you get. If the file comes out in the format that you want, then you're done.

KJ

With VHDL you can write binary files. This is the default. If you write t a binary file, this will be in a machine-specific binary format that wil be difficult for a human to read, even with a hex-capable file editor.

If you need a file that humans can read, use text files via STD.TEXTI package procedures, as advised above.