best way to perform multiplies in vhdl

i am trying to implement an image convolution filter that has negative values in it on a spartan IIe fpga. So i need to perform (for instance) A*B + C*D where A,B,C,D are all signed numbers in the ieee std logic int range. what is the best way to implement this? It seems that the way i am doing it now (using std_logic_vector) fails for negative values of the filter coeffs. can anyone give a suggestion how to fix this (the best way to code it in vhdl). What is the best way to do a numerical comparison (ie. A < B in vhdl (that is also synthesizeable), where A,B are signed integers)

thanks