I had the same problem, the answer from Altera is:
This message is being incorrectly printed. It is a bug that it is printed, and it has been corrected (by removing the message) in Quartus II 5.1 SP1. Ignore the message -- your design functionality and optimization are fine.
Basically our most recent FPGA families (Stratix, Stratix II, Cyclone, etc.) use a different method of storing delay information for optimization during the fitting procedure. This message says that new method is not being used. For APEX that is expected -- it uses a different method, and always will.
Regards, Vaughn Betz [v b e t z (at) altera.com]
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