Hi everybody,
I get this warning under Quartus 5.1 : "Performance of this circuit may degrade because the Fitter Delay Information is not loaded"
The FPGA is an ACEX EP1K30TC144-3...
I don't know what this warning is and how to load the correct Fitter Delay Information File ?
Thanks Best Regards.
I had the same problem, the answer from Altera is:
This message is being incorrectly printed. It is a bug that it is printed, and it has been corrected (by removing the message) in Quartus II 5.1 SP1. Ignore the message -- your design functionality and optimization are fine.
Basically our most recent FPGA families (Stratix, Stratix II, Cyclone, etc.) use a different method of storing delay information for optimization during the fitting procedure. This message says that new method is not being used. For APEX that is expected -- it uses a different method, and always will.
Regards, Vaughn Betz [v b e t z (at) altera.com]
schrieb im Newsbeitrag news: snipped-for-privacy@z14g2000cwz.googlegroups.com...
Have something to add? Share your thoughts — no account required.
Ask the community — no account required