programmable fir and simulation

For discussion I include the code of fir example.

-- This is a generic FIR filter generator

-- It uses W1 signed bit data/coefficients bits LIBRARY lpm; -- Using predefined packages USE lpm.lpm_components.ALL;

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL;

ENTITY fir_prog IS ------> Interface GENERIC (W1 : integer := 9; -- Input bit width W2 : integer := 18;-- Multiplier bit width 2*W1 W3 : integer := 19;-- Adder width = W2+log2(L)-1 W4 : integer := 11;-- Output bit width L : integer := 4; -- Filter length

-- for Mpipe = 1 output Y_OUT is OK (PT) Mpipe : integer := 3-- Pipeline steps of multiplier ); PORT ( clk : IN STD_LOGIC; Load_x : IN STD_LOGIC; x_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0);

-- c_in : IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); -- (PT) y_out : OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0)); END fir_prog;

ARCHITECTURE arch_fir OF fir_prog IS

SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0); SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0); SUBTYPE N3BIT IS STD_LOGIC_VECTOR(W3-1 DOWNTO 0); TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT; TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT; TYPE ARRAY_N3BIT IS ARRAY (0 TO L-1) OF N3BIT;

SIGNAL x : N1BIT; SIGNAL y : N3BIT; SIGNAL c : ARRAY_N1BIT; -- Coefficient array SIGNAL p : ARRAY_N2BIT; -- Product array SIGNAL a : ARRAY_N3BIT; -- Adder array BEGIN

Load: PROCESS ------> Load data or coefficient BEGIN WAIT UNTIL clk = '1'; IF (Load_x = '0') THEN -- load coefs from X_IN input (PT) c(L-1)

I'm guessing that since your flip-flops are not initialized upon reset, what you are seeing is the time it takes for your filter taps (and coefficients?) to settle down with valid values. For many designs, this type of behavior is not a problem. - but you'll have to be the judge of that for your situation.

Of course. It often helps in diagnosing problems.

Once posted to usenet, you have little control of the code. You can place a copyright on it, but enforcement can be near impossible.

Marc