Anomalous Behaviour of Quartus 4.0 simulation

I have encountered strange inconsistensies in simulation results of my design. First of all, the simulation results drastically change if a dummy port is connected or disconnected to an output of some logic block (my design is done fully in BDF).

While simulating, suddenly, after I changed a name of one signal, other signal's values have drastically changed. I couldn't trace the problem but after I have disconnected an output port from that signal it suddenly started working as before and its values actually appeared on the disconected output port and showed up in the simulation.

I have a 4 bit register that clocks-in a value. For some reason, again after modofying unrelated block, the register stopped clocking-in the value and its output was always stuck at 0000. After endless hours I just decided to add another register in parallel to see if it will clock-in the data. To my surprise, the original register suddenly started working again.

I am currently stuck with another strange problem and feeling a little frustrated...

Has anyone expereinced anything similar ??? Is there something wrong I might be doing ?

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vadim
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