Hello,
I am getting follwing warning while I simulate (Post Lay out simulation) my design using Modelsim
# ** Warning: */DFC1B SETUP Low VIOLATION ON D WITH RESPECT TO CLK; # Expected := 1 ns; Observed := 0 ns; At : 67127 ns # Time: 67127 ns Iteration: 4 Instance: /testbenchcmedmain/uut/mdec2_u2_reg_0
I was not getting this warning in Post Synthesis simulation but I am getting this warning in post layout simulation.
I am using Actel Libro IDE for the synthesis and lay out.
Is this warning related to setup time?