regarding the post PnR timing simulation.....

hi all,

i have done the post place and route timing simulation for my design. i am getting the following warnings . there is a setup time voilation but can any one explain what this statment means

Time: 4785 ps Iteration: 2 Instance: /sts3c_top_tb/dut/ deframer_inst_fifo_inst_bu236 # ** Warning: /X_SFF SETUP High VIOLATION ON SRST WITH RESPECT TO CLK; # Expected := 0.748 ns; Observed := 0.653 ns; At : 4.785 ns

is that my data is arriving early than the expected ... can any one explain me what that warnings means and how can i make sure in my design to avoide this kind of warning .. that does this kind of warning do matter when i am loading my design into silicon. as my design is not working on the actual silicon.

thanks ....

regards kil

Reply to
kil
Loading thread data ...

Hi, SRST signal changes its value to close in time to the active edge of clock CLK. It should be changed at least 0.748 ns before the active edge. But the change appears

0.653 ns before the active edge. The violation is detected at 4.785 ns simulation time (It is probably beginning of the simulation).

You are probably applying reset in the testbench at the same time when an active clock edge appears. The reset should be applied some time after an active clock edge. This is the most frequent reason of that. There are also many other possible reasons: - you are clocking the design with too high frequency. - the clock is significantly delayed in you design (big clock skew) - the reset signal is crossing different clock domains..etc.

Best Regards, Steve

formatting link

Reply to
Slawek

thanks mr steve..

i am usign clokc of 155Mhz(6.43 ns) and in my testbench i am doing reset after 100 ns (intially it is '0' then it is '1' after 100 ns delay) is this the reason for my warnings. but this is in testbench and actual design should not be get effected by this right and it may not effect in the actual silicon....

Clock Report:

************************** Generating Clock Report **************************

+-------------------------+----------+------+------+------------

+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------ +-------------+ | clk155p52 | Local | | 100 | 1.054 | 4.249 | +-------------------------+----------+------+------+------------ +-------------+

The Delay Summary Report

The SCORE FOR THIS DESIGN is: 164

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

The AVERAGE CONNECTION DELAY for this design is: 1.053 The MAXIMUM PIN DELAY IS: 4.590 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 2.960

Listing Pin Delays by value: (nsec)

d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >=

5.00 --------- --------- --------- --------- ---------

--------- 899 217 82 116 34

0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.

-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels

-------------------------------------------------------------------------------- TS_clk155p52_p = PERIOD TIMEGRP "clk155p5 | N/A | N/A | N/A 2_p" 6.430 nS HIGH 50.000000 % | | |

-------------------------------------------------------------------------------- TS_clk155p52_n = PERIOD TIMEGRP "clk155p5 | 6.430ns | 6.091ns | 6 2_n" 6.430 nS HIGH 50.000000 % | | |

--------------------------------------------------------------------------------

All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 mins 16 secs Total CPU time to PAR completion: 2 mins 44 secs

Peak Memory Usage: 322 MB

Placement: Completed - No errors found. Routing: Completed - No errors found. Timing: Completed - No errors found. this what the timing report after place and route.......

regards kil

Reply to
kil

Hi, as I mentioned there are many of possible reasons.

  1. Regarding the timing violation. You can check inputs of the /sts3c_top_tb/dut/deframer_inst_fifo_inst_bu236 flip-flop and track the change to find its source. However, such violation at the beginning of the reset may not be relevant.

  1. I am guessing but if your design incorporates LVDS transmission module working on both clock edges (DDR) quality of the clock is essential, for instance jitter, duty cycle, phase shift (comparing to clock phase in external receivers and transmitters) etc. Such things are not modeled very well in simulation and you may be surprised why it is working in simulation but not in the real silicon.

This is all what I can guess without knowing your design.

Best Regards, Steve

formatting link

--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

--------------------------------------------------------------------------------

Reply to
Steve

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.