Escenario : Need a clock system with range from ~50Mhz to 150Mhz with as much granularity as possible to drive an FPGA.
Could anyone please suggest options on how to better implement this clock system.? I've looked at programmable clocks from Cypress, Maxim-ic, but these require some I2C or 2-wire interface, and I don't have a microcontroller on board, just the FPGA so I'd need to put a I2C core... . I've looked at using the PLL core in the FPGA (Actel in this case), but I find the documentation about it to be extremely poor as to how to really implement it.
By the way, if anybody has had experience using the PLL core in Actel, could you please give a simple example on how to use the core generated by "Actgen." I've read the document on "PLL dynamic reconfiguration using JTAG," and I still don't understand completely....
Thanks in advance,