...
... For much of the time precision, latching the value of the DCM's delay line could give extreme input resolution (resolution of a single tap though the accuracy would be slightly worse than one tap). I'd love to get down to ~100ps accuracy for sampling some very low frequency signals. If I could provide multiple phase-shifted outputs based on multiple phase-sampled inputs, I'd be in FPGA heaven. It seems like throwing a SERDES at a signal that toggles well under 100MHz is overkill especially when we need the low cost parts. For now, it's a matter of sampling on several phases to get a
4x or 8x the master clock resolution. Adequate, perhaps, but not awe-inspiring.