Input clock of PLL

Before going into details I want to explain the background:

I am using an FPGA to deal with signals coming from an external USB transceiver.

This USB transceiver has an 16bit parallel interface. The data coming into the FPGA are synchronous to a clock which is generated by the USB transceiver.

I use that transceiver clock to feed my PLL (input frequency 30MHz).

Of course there is also the other direction that is I have to send data back to the USB transceiver. These data have to be synchronous to the transceiver clock.

Now I ask myself which clock to use correctly to generate data to send back to the USB transceiver.

When I use this input clock I would like to know what timing constraints I have to consider for the data I send back to the transceiver so that I do not violate Tsu, Th ... Or would it be more preferable to use a different clock (1:1) maybe coming out of the PLL ?

Any ideas are highly appreciated.

Rgds André

Reply to
ALuPin
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hi,

Before giving a suggestion, i assume the following

1.USB transceiver has got separate tx and rx clocks. 2.USB transceiver gives out data w.r.t the tx clock to FPGA 3.USB transceiver receives data in w.r.t the rx clock from FPGA

In that case I would suggest using a clock output of PLL. The advantage of using a PLL is that, it will filter out jitter, and also compensates for the skew through clock net(zero delay). But there will be an offset between clock input to PLL and clock output from PLL. That offset value should be used in giving Tsu, Th constraints to data input registers. since it's only 30MHz, there won't be much problem with this offset. But the delay on board from USB transceiver also need to be taken into account.

So inside FPGA, only the clock out from PLL can be used. The same clock can be driven out as a rx_clock, or can be used for outputing data towards USB.

Reply to
Bala_k

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