PLL and clock in altera cyclone 2 fpga

Hi,

I am using a cyclone 2 FPGA, and have a propagation delay warning in one of the megafunction's, lpm_divide. If we use a slower clock to this block it will work properly, but the system clock is 27MHz which is too fast for the bit width's of the numerator and denominator even with pipelining selected in lpm_divide. I haven't used the cyclone PLL before, but its lowest output frequency is 10MHz which is still a bit higher than I would like to run the lpm_divide at. I could add another external crystal, but I was wondering if it is possible to generate a logic clock inside the FPGA by using flipflops etc. I have been told that this is a bad idea to clock this way due to logic glitches, but am not sure why or if that is true?

cheers, Jamie

You can use the megawizard to change the PLL, I think it allows multiple clock outputs (in Cyclone 3 more than 2, but I think it was at least 2 in Cyclone 2, too).

How fast do you need to divide? Once I had a similar problem, but with LPM_MULT, because I needed some large bitwidths, but only at low frequency, so I implemented it serially myself like this, for signed multiplications:

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all;

ENTITY Multiplier IS PORT( reset : IN STD_LOGIC; Clock : IN STD_LOGIC; Factor1In : IN STD_LOGIC_VECTOR (23 downto 0); Factor2In : IN STD_LOGIC_VECTOR (15 downto 0); ProductOut : OUT STD_LOGIC_VECTOR (23 downto 0); StartMultiplication : IN STD_LOGIC; Completed : OUT STD_LOGIC ); END Multiplier;

ARCHITECTURE logic OF Multiplier IS

SIGNAL Factor1 : SIGNED (39 downto 0); SIGNAL Factor2 : STD_LOGIC_VECTOR (15 downto 0); SIGNAL Counter : integer range 0 to 16;

type StateType is (WAIT_FOR_START, ADD, COPY_OUTPUT);

SIGNAL Product : SIGNED(39 downto 0); SIGNAL State : StateType := WAIT_FOR_START;

BEGIN

PROCESS (reset, Clock) VARIABLE temp : STD_LOGIC_VECTOR(39 downto 0); BEGIN IF (reset = '1') THEN State