I'm looking to implement four, 150 tap FIR filters in an Actel MX series FPGA. The filters I'm designing are 16 bit input, 16 bit coeffienencs, and1khz sample rate. FPGA will be clocked with a 10MHz clock and will have a state machine to retrieve the samples from the A2D following a 1khz interrupt.
How do I estimate the resource requirements to implement such a beast? Any special hurdles in implelenting this type of thing in a Actel MX series FPGA?
MX series is a fixed quantity and cannot be changed.