Hi;
Can anyone give a instruction on how to implement "altclklock" (PLL) for EP20K200E fpga in details? PLL input clock is 33Mhz. I want PLL's output clock0 is 33Mhz and clock1 is 33/2Mhz, using internal feedback. (No external feed back).
I can not make it compiled in QuartusII 3. The error message is something like "locked output must drive (positively) only clock pin or port".
Thanks
--ZL