Hi Fellow, I want to send data to FPGA and store in register in FPGA sequentially. In my design it is required to take 12 input from the data bus in 12 different clock pluse one by one then I have to start processing data in FPGA and then the result after performing calculations is to be taking out of FPGA. The problem which I am facing is syncronization of clock. B/C I am downloading data using C code. In FPGA I have defined 100 MHz clock frqeuency and my processor is working on 2 GHz. SO if I have to send
12 data signals to FPGA then it will be taking input much slowly as compared to PC speed. And in my design Clock cycle is important because I am using clock cycle count's to do different things. Could any body please tell me how to synchronize the PC and FPGA internal clock. Do I need to use SLEEP command in C program to do that . And one thing more that C instruction also uses more then one clock cycle to perform particular task.Any help in this regards would be appreciated.
Regards
Isaac