I know this topic has been discussed before, but i am looking for some ideas. My design is synchronous, I use ISE8.2.02 XST and ModelSim, I have a lot of signed logic; I get different results from behavioral and post-Route simulations. I paid attention to the reset condition, in fact the data are ok after the first stage of the circuit. I tried to delay the data compared to the clock with no success. I noticed that at the first rising edge of the clock most signals are x in the post-P&R simulation, while they are defined in the behavioral simulation. Any advice before bringing out every meaningful signal in the implementation process ? Any known bug in the simulation models of the xilinx primitives (multipliers, BRAMs, etc) ?
Tullio