Still more problems with FIFOs. Today I tried to use the Coregen Wizard to generate a FIFO, hoping that the generated FIFO would be better than the one in my previous post.
I clicked on Project, New Source, IP. Clicked on Synchronous FIFO, Blocked Memory,32 Width, 2048 Depth (thinking one BRAM).
I have some extra package that an FAE installed so I don't know if this is available to the Web Pack crowd.
I tried to run a Waveform for this generated FIFO and got a message TestBench Waveforms are not currently supported for Arch Wizard or CoreGen sources.
I have seen this problem before and generated a top level design with the generated FIFO as a component. This involves some cut and paste of the component and instantiation of the VHDL FIFO code into the top level, basically re copying the entity ports, the component declaration, and the instantiation of the FIFO in the top level. You have to get rid of the word "wrapped". I'll put this code at the end.
Same problem however. The Simulate Behavior Model runs OK. The Simulate Post-Place and Route VHDL Model does not.
Brad Smallridge b r a d @ a i v i s i o n . c o m
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
entity top is port ( clk: IN std_logic; sinit: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic); end top;
architecture Behavioral of top is
component fifotest port ( clk: IN std_logic; sinit: IN std_logic; din: IN std_logic_VECTOR(31 downto 0); wr_en: IN std_logic; rd_en: IN std_logic; dout: OUT std_logic_VECTOR(31 downto 0); full: OUT std_logic; empty: OUT std_logic); end component;
U0 : fifotest port map ( clk => clk, sinit => sinit, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty);