Hi all,
I have a design where MicroBlaze isn't the top level of it.
I have simulated the behavioral model with ModelSim SE 5.6f and it works fine but when I implement and download to the FGPA it doesn't work, so now I want to simulate the Post-Place & Route model too see if there's any timing wrong.
Due to my MicroBlaze desing isn't the top level, XPS doesn't allow me generate the behavioral model, so I have to do it manually. That's the way I have done the behavioral model simulation.
So I have a Project Navigator design with various components which one of them is the MicroBlaze designed in XPS. In the testbench I use a configuration block where I assign the code that needs to be inside the blockram of MicroBlaze. Since MicroBlaze isn't my top level this configuration block has the next aspect:
configuration testbench_conf of system_tb_system_vhd_tb is for behavior for uut1 : top_level for structure for uut2: mb_blaze for structure for all: instr_mem_wrapper use configuration work.instr_mem_conf; end for; end for; end for; end for; end for; end for; end testbench_conf;
The problem comes here. When I ask ISE to simulate the P&R model it generates a file called "top_level_timing.vhd" which hasn't got any hierarchy, so obvioulsy the configuration block generates some compilation errors.
Is there any other way to assign the contents of the instruction set to the blockram of MicroBlaze?
Any other idea to avoid this error?
I am not used to working with configuration blocks, so the solution might be obvious.
Thanks in advance,
Arkaitz.