You are correct. When you do your design, you should know the clock frequency (or frequencies) that your design needs to operate at, as well as the requirements at the I/O pins, such as setup and hold times with regard to other I/O pins, and usually clock pins.
Together, these timing requirements are referred to as "timing constraints" by the FPGA implementation software.
So you pass your logical design plus these constraints to the implementation software, and the end result is hopefully a placed and routed design, plus a timing report. If all went well, the timing report tells you that all your constraints have been met. This would be "closure".
Providing that your design is logically correct, and you have timing closure, you are ready to try out your design in an FPGA.
If you don't have timing closure, there is little point in running your design, since although it still may work (because the device you are using might be better than average, or it is a cold day, or a full moon), you could not predict whether the design would run in the next chip you try.
If you dont have timing closure, there are several hings you can do:
1) Run the implementation tools again. Some tools have some randomness in their operation, and you might be lucky.
2) Figure out what paths did not meet timing constraints, and change your design to make these paths take less time. I.e. less logic, more pipeline stages
3) Change to a faster FPGA
4) Change you clock rate, and the constraints
Note that timing closure does not guarantee that your design will work. I have seen many designs where the constraints did not cover all paths in the design. The implementation tools are notorious for reporting that your design meets timing, but fails to tell you that only 30% of your paths had timing constraints. The rest of the paths MUST have some timing requirement, but you forgot to include it in the constraints list.
There are no stupid questions, only stupid answers.
=================== Philip Freidin firstname.lastname@example.org Host for