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Best Place and Route

Hi, Recently I am doing P&R for my FPGA Design. Unfortunately, whenever I using the auto P&R provided in the software, I wont find a satisfactory result since some internal flip-flops alway have timing violations due to the routing, i.e. D-flipflop with setup time violation with respect to CLK, etc. So I doubt that whether a manual P&R is possible under this circumstance. If yes, what are the golden rules to do this manual P&R without any tool like floorplanning ? I will assign the gate/cells one by one into the FPGA.

Reply to
Wong
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Howdy Wong,

Your description is not detailed enough for anyone to give you a good answer. A copy of *part* of the detailed timing report would go a long ways towards showing what is wrong (hopefully it shows clock rate as well as routing and component delays).

Your problem could be caused by any number of issues, from too many levels of logic to plain old poor placement (either due to the device being full, too empty, or just bad decisions by the placer), and all the stuff that goes between. Or maybe it's close and just needs a different seed.

Good luck,

Marc

Reply to
Marc Randolph

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