Post PAR Simulation and Actual FPGA results differ

Hi All, I am currently developing for Xilinx SPARTAN3 FPGA. I have a design in which a FSM asserts a clock enable signal for few registers (all registers use the same clock-enable) for 1 clock cycle. My post place and route simulation shows correct operation of the design i.e the registers are updated correctly. However when I run the design on actual FPGA the registers are not updated and design doesn't behave correctly.

I extended the clock enable to 2 clock cycles and this makes the design run correctly on the FPGA.

I have done post PAR timing analysis and don't get any timing errors. I am also clocking the device at half the clock speed that the design can be run at. I am not sure what the problem is. Would anybody please be able to tell me what the problem might be.

Thanks for your help. Sudhir

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Have you checked your setup/hold timings of your FPGA inputs ? Are you simulating them in an appropiate way ?

Rgds Andr=E9

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Are you giving the state machine a clean synchronous reset? Are all inputs to the state machine properly synchronized? You might add logic on a test pin to indicate if the state machine enters an illegal state such as zero hot or 2-hot.


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Jeff Cunningham

Thanks for the reply. Yeah I am giving the FSM a clean sycnhronous reset and the inputs are all sychronous. I'll test for the FSM going into illegal state.


Jeff Cunn> Are you giving the state machine a clean synchronous reset? Are all

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You could also use Chipscope Pro to monitor the signals on chip. That may help you see what's going wrong. You can get free evaluation version on the Xilinx web site

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juendme wrote: However when I run the design on

Did you check that ALL you inputs to the FSM (including indeed the Clock Enable !) are properly re-synchronized ? This is probably the most common design error. I see it everyday.

Hope this helps,


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