Hi guys, I am developing a project that involves tens of 8 bit buffers. I am designing it with regular TTL logic but maybe in the future I will use FPGA if the project works. Well, I know developing with FPGA is better but I just don't have the initial investment and I have a lot of experience with TTLs.
I can design it either with 74ls373 or 74ls374. If I use 74ls374, they will not share a common clock. I am wondering which design is easier to transfer to FPGA or CPLDs. I have little experience with FPGAs. What I know is that they like registers with common global clock. Please inform me... Thank you.
vax3900