Hi,
in my design I would like to have the possibility to switch beetween two clock signals: 'clk' (this is my main clock) and 'ext_clk' (the second,
external clock) and the output clock is 'clk_out'. It all depends on one signal - let's call it 'temp'. 'Clk_out' is then used in the sensitivity list of some process ("process(clk_out) ..."). But when I code it in VHDL like this:
clk_out
Go to the Xilinx website xilinx.com Enter six easy pieces in the search window Open the TechXclusive article with that title Scroll down to #6
and you find a circuit that allows you to switch between two unrelated clock frequencies, and do the switching asynchronously to either clock.
The only limitation is that both clocks must be free-running, since you cannot switch away from a locked-up clock.
Peter Alfke. Xilinx Applications
You can also use this insanely unwieldly URL:
intantiate a BUFGMUX (from ISE tepmlates)
Library UNISIM; use UNISIM.vcomponents.all;
-- BUFGMUX_VIRTEX4: Global Clock Buffer 2-to-1 MUX -- Virtex-4 -- Xilinx HDL Language Template version 8.1i
BUFGMUX_VIRTEX4_inst : BUFGMUX_VIRTEX4 generic map ( INIT_OUT => 0, -- Inital value of 0 or 1 after configuration PRESELECT_I0 => FALSE, -- TRUE/FALSE set the I0 input after configuration PRESELECT_I1 => FALSE) -- TRUE/FALSE set the I1 input after configuration port map ( O => O, -- Clock MUX output I0 => I0, -- Clock0 input I1 => I1, -- Clock1 input S => S -- Clock select input );
-- End of BUFGMUX_VIRTEX4_inst instantiation
Regards, Aurash
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