Has anyone encountered this problem with Altera/Quartus?
I have a set of cascaded registers which can either be implemented using cascaded lpm_ffs or an altshift_taps unit. I have a main clock and an enable signal with a clock enable multicycle setting of 5. If I implement the registers using lpm_ffs then the required clock setup time is correctly stated in the timing analyzer as being 33.33ns (main clock is at 150MHz -> 6.666ns period, 5*6.666ns = 33.33ns). However if I implement the registers using altshift_taps the required clock setup time is stated as being 6.666ns in the timing analyzer section of the compilation report, ie the clock enable multicycle setting of 5 has been ignored. I first noticed this type of problem when I had the auto shift register replacement option in the analysis and synthesis settings turned on, which converts lpm_shiftregs to altshift_taps. I can provide design files if anyone wants to try and help, I have waited 5 days for a response from Altera support.