Hi,
I'm trying to dynamically reconfigure a Virtex-4 FPGA, by following the example of XAPP 290. I'm following the module-based partial reconfig flow, but since the tools don't support generation of partial bitstreams, I use difference-based bitstreams to reconfigure the FPGA. The generation of full and partial bitstreams works perfectly, and I have no problem when downloading the initial bitstream to the chip. However, when I try to download a partial bitstream, I have the following warning message :
Warning:iMPACT:2218 - Error shows in the status register, release_done bit is NOT 1.
The FPGA pauses (it seems that the outputs are 3-stated) until I click ok "ok". When I read the status register after that, the done pin has the correct value.
Does anyone have an idea about the cause of this warning ?
Thanks,
Denis
PS : I'm using a VIRTEX-4 LX25 on an Avnet board, and I'm using a parallel cable IV in Boundary scan mode. I'm working with ISE 7.1 SP3. Here are my bitgen -g options :
-g ActivateGCLK:Yes
-g ReadBack
-g DebugBitstream:No
-g CRC:Enable
-g ConfigRate:4
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:PullUp
-g ProgPin:PullUp
-g DonePin:PullUp
-g DriveDone:No
-g PowerdownPin:PullUp
-g TckPin:PullUp
-g TdiPin:PullUp
-g TdoPin:PullNone
-g TmsPin:PullUp
-g UnusedPin:PullUp
-g UserID:0xFFFFFFFF
-g DCMShutDown:Disable
-g DisableBandgap:No
-g StartUpClk:JtagClk
-g DONE_cycle:4
-g GTS_cycle:Keep
-g GWE_cycle:Keep
-g LCK_cycle:NoWait
-g Match_cycle:NoWait
-g Security:None
-g Persist:No
-g ActiveReconfig:Yes
-g DonePipe:No
-g Encrypt:No