partial reconfig of Virtex-4 : iMPACT warning makes the chip pause

Hi,

I'm trying to dynamically reconfigure a Virtex-4 FPGA, by following the example of XAPP 290. I'm following the module-based partial reconfig flow, but since the tools don't support generation of partial bitstreams, I use difference-based bitstreams to reconfigure the FPGA. The generation of full and partial bitstreams works perfectly, and I have no problem when downloading the initial bitstream to the chip. However, when I try to download a partial bitstream, I have the following warning message :

Warning:iMPACT:2218 - Error shows in the status register, release_done bit is NOT 1.

The FPGA pauses (it seems that the outputs are 3-stated) until I click ok "ok". When I read the status register after that, the done pin has the correct value.

Does anyone have an idea about the cause of this warning ?

Thanks,

Denis

PS : I'm using a VIRTEX-4 LX25 on an Avnet board, and I'm using a parallel cable IV in Boundary scan mode. I'm working with ISE 7.1 SP3. Here are my bitgen -g options :

-g ActivateGCLK:Yes

-g ReadBack

-g DebugBitstream:No

-g CRC:Enable

-g ConfigRate:4

-g M0Pin:PullUp

-g M1Pin:PullUp

-g M2Pin:PullUp

-g ProgPin:PullUp

-g DonePin:PullUp

-g DriveDone:No

-g PowerdownPin:PullUp

-g TckPin:PullUp

-g TdiPin:PullUp

-g TdoPin:PullNone

-g TmsPin:PullUp

-g UnusedPin:PullUp

-g UserID:0xFFFFFFFF

-g DCMShutDown:Disable

-g DisableBandgap:No

-g StartUpClk:JtagClk

-g DONE_cycle:4

-g GTS_cycle:Keep

-g GWE_cycle:Keep

-g LCK_cycle:NoWait

-g Match_cycle:NoWait

-g Security:None

-g Persist:No

-g ActiveReconfig:Yes

-g DonePipe:No

-g Encrypt:No

Reply to
Denaice
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It is normal, DONE pin is not modified during the partial reconfiguration.

In ISE 7.1 partial reconfiguration on Virtex4 is not well supported. It works only with very small designs making some manual work on the FPGA Editor.

Regards

Javier Castillo

Reply to
Javier Castillo

Thanks for your help.

I have one more question : Is there a mean to reconfigure the virtex-4 (with partial bitstreams) without pausing it, or do we have to use full bitstreams ?

Thanks in advance,

Denis

Reply to
Denaice

"Denaice" schrieb im Newsbeitrag news: snipped-for-privacy@g49g2000cwa.googlegroups.com...

it should be possible, but may be very tricky antti

Reply to
Antti Lukats

I'm not sure what you are asking. When you reconfigure the FPGA with a partial bitstream the FPGA is not paused, the not reconfigured part is working during the partial reconfiguration. That is the reason because you can reconfigure one part of the FPGA using the ICAP port. For this type of questions I recommend you to use the partial reconfiguration mailing list.

Regards

Javier

Reply to
Javier Castillo

Well, for the moment, I'm not reconfiguring through ICAP with a PPC or Microblaze. I'm only trying to reconfigure in JTAG by the remote PC, but it seems - obviously - that the FPGA pauses when reconfiguring (because in my design, the leds which, should continue to blink, are shut down).

I don't know....

Reply to
Denaice

Yes, impact send a command to stop the FPGA. One thing you can do it to use the SelectMap interface or send the bitstream to the jtag without using Impact. It is not very difficult to make a program in C to program the FPGA using the JTAG.

Javier

Reply to
Javier Castillo

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