Hello I am porting a PCI design from an Altera Stratix to a Xilinx Spartan3 and I am experiencing timing problems. I think the design is a bit underconstrained. Can somebody give me ISE equivalents for these Quartus constraints:
FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER TH_REQUIREMENT (probably something like IOBDELAY) DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
I am also trying to figure out how to separate the clock-to-pad delays for the output enable and the output register paths. I only find the OFFSET = OUT ... AFTER constraint. I am using a FROM-TO but I feel this is not quite right.
Thanks