Hi Whenever I try to map an EDK simulation after exporting it to Project Navigator ISE 5.2 version, i get this error for a microblaze system. Can someone help me with this
thanx Paraag
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=mblaze, RLOC=R-15C10.S1) which require the combination of the following symbols into a single SLICE component: FLOP symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/i_abus_dff" (Output Signal = _n0099) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/muxcy_i/O) LUT symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/i_alu_lut" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/alu_addsub) XORCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/xor_i" (Output Signal = d_lmb_lmb_abus) MULTAND symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/mult_and_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i1/di) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/pre_muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/pre_muxcy_i/O) The settings of the two configuration muxes CY0F and CY0G don't agree. Please correct the design constraints accordingly. ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=mblaze, RLOC=R-16C10.S1) which require the combination of the following symbols into a single SLICE component: FLOP symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/i_abus_dff" (Output Signal = _n0099) MUXCY symbol "mblaze/microblaze_0_i/decode_i/new_carry_muxcy" (Output Signal = mblaze/microblaze_0_i/decode_i/new_carry_muxcy/O) XORCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/xor_i" (Output Signal = d_lmb_lmb_abus) LUT symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/i_alu_lut_2" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/alu_addsub) MULTAND symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/mult_and_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/di) MUXCY symbol "mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/muxcy_i" (Output Signal = mblaze/microblaze_0_i/data_flow_i/alu_i/alu_bit_i0/muxcy_i/O) The settings of the two configuration muxes CY0F and CY0G don't agree. Please correct the design constraints accordingly. Problem encountered during the packing phase.