VHDL : Use concatenation on port mapping

Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);

Reply to
Georgios Sidiropoulos
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Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress =>

packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);

Reply to
Georgios Sidiropoulos

You could use some concurrent assignment in which you perform the concatenation.

PORT MAP ( data =3D> ls_data_concat ....)

ls_data_concat

Reply to
ALuPin

you can't concat there.. you have to do it to another variable first

Simon

statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress =>

packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);

Reply to
Simon Peacock

PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, -- illegal. see below use ranges wren => CAV or DAV, -- illegal. maybe in VHDL-2006 wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0 );

Slicing arrays (of course insert the correct dimensions): PacketRAM: packet_dpram PORT map ( data(3 downto 0) => CAV, data(7 downto 4) => DAV, data(15 downto 8) => KDATA,

When doing this, always map all elements of data and map all elements of data consecutively.

Cheers, Jim P.S. You might also try posting in comp.lang.vhdl for VHDL questions.

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Jim Lewis
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Reply to
Jim Lewis

Cool Jim, Can slicing arrays be done on Verilog. I had XST warning on "unused" bits after a multiply, and indeed, some of the lsb bits were not used because they were truncated on purpose. I was wondering whether data slicing in Verilog was possible to alleviate dealing with the XST warning.

-Newman

Reply to
Newman

I was porting a code form a friend who was working with Altera Quartus. That is where i saw the use of logic operations and concatenation within port mapping statements. Perhaps Quartus is not so strict with the syntax. Thanks very much.

Reply to
Georgios Sidiropoulos

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