Can someone use logic operations or concatenation within port mapping statments on Xilinx ISE? for example: PacketRAM: packet_dpram PORT map ( data => CAV & DAV & KDATA, wren => CAV or DAV, wraddress => packet_wraddress, rdaddress => packet_rdaddress, wrclock => LHC_CLK, rdclock => INT_CLK, q => packet0);
- posted
18 years ago