Please help with Xilinx ISE Schematic question

I need help in creating constants to be used with schematic capture.

In previous versions of Xilinx ISE I used to create schematic symbols for constants (i.e. 0xA5) by creating a schmetic with 8 buffers. The inputs were connected to gnd or vcc to create the constant. The outputs of the buffer were connected to a bus CONST(7:0).

Then I could use this constant anywhere in my schematic by inserting this part.

I tried this on the latest ISE 6.1 and got the following error when I compiled.

ERROR:Xst:1539 - C:/Projects/DemoTop.vhf line 122: Formal port in component must be an identifier.

Here is the DemoTop.vhf output:

XLXI_30 : const8_80 port map (Const(7 downto 0)=>XLXN_12(7 downto 0));

Why doesn't this work anymore? Is there a better way to create a constant. I know that Altera has a constant macro. Is there any easy way in Xilinx.



P.S. Please post the answer in the newsgroup rather than emailing it.

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My guess would be it's an ECS (schematic editor) bug. I'd say 90% of the bugs I've found are with ECS. One that I found in 6.1i was that if you put the attribute "uselowskewlines" onto a net, synthesis chokes because the vhf output file misspells the key word "SIGNAL" as "SIGANL".

Another way to create a c> I need help in creating constants to be used with schematic capture.

Reply to
Marc Guardiani

you found a funny bug, the same problems appears even if you write the constant in VHDL file and instantiate that in ECS toplevel. the problem doesnt happen if you use verilog as simulation language for your project. So not sure if the problem is in ECS or XST. but its a pretty serious problem-bug in the tools.

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Reply to
Antti Lukats

VHDL-87 did not allow constants to be connected to ports.

VHDL-93 does.

Is there a switch that turns VHDL-93 on?

To be compliant with the newest VHDL RTL synthesis standard IEEE P1076.6-2003, Xilinx needs to support this.

If they don't, the work around is to create a signal, and assign it a value (in the concurrent part of code since often initializations of signals are not supported by synthesis).

signal sig_XLXN_12 : std_logic_vector(7 downto 0) ;

. . .

sig_XLXN_12 I need help in creating constants to be used with schematic capture.

Jim Lewis
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Jim Lewis

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