Designing a simple PLB master using EDK 6.3i

Hello,

I designed a module that issues writes and reads to the PLB bus using IPIF interface from the "Create Peripheral" wizard in EDK's XPS. I have issued requests per the guidelines in the PLB documentation

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) and the README.txt that comes with the "Create Peripheral" wizard. Specifically, I have been using the waveforms on pages 116 and 117 as guidelines. The main difference is that my implementation issues single beat writes and reads. Nonetheless, I'm using the write/read requests in a similar manner as the waveforms in the PDF: I'm hold the request signals high until the MstLastAck, MstTimeOut or MstBusError goes high. All the data, BE's, address signals, etc. have been set-up before the request signal is asserted. The problem I'm encountering is that the plb_ipif module in my_plb_master pcore doesn't respond accordingly. For instance, the signals M_request, M_RNW, M_BE do not change appropriately. The slave attachment signals also do not toggle as demonstrated on the diagrams. Is anyone aware of any more documentation about the specifics of the timing for all these signals. With only two pages of waveforms (as compared to the 14+ pages of diagrams for the slave interface), it is difficult to know what I'm doing wrong (assuming the plb_ipif module is bug-free). Even better, does anyone designed plb masters modules? Anything useful gleaned from that experience?

Thanks in advance,

NN

Reply to
Nju Njoroge
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Nju,

I've been designing master PLB master modules using the PLB IPIF for quite a while now and, like in your case, the only think I could rely on were the two diagrams you referreded to in your message and the simulation results. I have to say that I did not follow the design flow suggested by Xilinx because I just instatiated the PLB IPIF inside my code and I did not use the Peripheral wizard.

I think that the timing reported in those two diagrams is not correct becasue the signls Bus2IP_Cs and Bus2IP_CE are always asserted at the same point in time but the signals Bus2IP_RdCe, Bus2IP_WrCe, Bus2IP_RdReq and Bus2IP_WrReq, althought are always asserted at the same time, are alwas at least one clock cycles delayed respect to the previous two.

To be honest, I do not think that that module is bug-free but so far it seem to behave correctly in our application.

If you can be more specific about your problem maybe I can help you a little more.

Regarding the documentation, I do not know if something more detaild exist.

Regards,

Andrea Sabatini

Reply to
Andrea Sabatini

Hello Andrea,

Thank for the response. I wrote a simple test pcore to get a feel for how the plb_ipif module should respond. Below is snippet of the main code. The summary of the code is that it issues a single beat write to an address, then issues a read to the same location. There is a little counter that waits after the reset signals have gone high before it starts the write/read requests. Note that the BE, Data, Addr, buses etc. are held constant well before the requests are made. Would you happen to have a simple example of PLB master you wrote that works? I would like to see the timing to get an idea why the M_Request and associated plb_ipif signals are not being triggered. Also, what version of plb_ipif are you using? We are using plb_ipif_v2_01_a (the one that has a master attachment).

Thanks,

Nju

reg [6:0] counter; wire counter_done;

// Logic for simple 7-bit coutnter always @(posedge Bus2IP_Clk) begin if(Bus2IP_Reset) counter[6:0]

Reply to
Nju Njoroge

Hello,

Thanks to Andrea's help, I was able to confirm that I was properly setting-up the master write/read requests signals . I was able to narrow done the problem to the slave to master attachment interactions in the plb_ipif. For instance, when the my user_logic module issues a master read, the master attachment issues a read on the PLB bus and it seems to be executing successfully (all the ACKS go high at the appropriate moment on the PLB bus). After the master read, the slave attachment is supposed to perform a write to the "local" memory in my user_logic module. The Bus2IP signals (like Bus2IP_WrReq) from the slave attachment, which are supposed to toggle during a slave attachment write, do not toggle. Likewise, for a master write, the slave attachment should perform a local memory read, which also fails (no activity on the slave Bus2IP_x signals), so the master write is never completed since the slave read is not performed. I looked at the internal plb_ipif signals in simulation (ModelSim), which show that sa2ma_x and ma2sa_x have activity, but the activity eventually leads to errors. In summary, the Master to PLB bus interactions seem actually okay, but there is some failure within the slave master attachments interactions (sa2ma_error signals is asserted during these failures), the whole transaction does not complete properly.

Has anyone encountered such issues? I haven't changed the inputs/outputs of the plb_ipif instantiation that the "Create/Import IP" wizard generated. Andrea said that she just instantiated the plb_ipif manually (i.e. not with the Wizard). Has anyone else had to adopt this approach to get a master plb module working?

Thanks,

NN > Hello Andrea,

Reply to
Nju Njoroge

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Reply to
Nju Njoroge

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