Yes. But normally there will be an arbiter, as there are two masters: microblaze (instruction) and microblaze (data). I do remember that some time ago, there was the option to avoid any of the two OPB, but at least from EDK 7.1 I cannot find it. (Will search a little, BTW)
Tool does,latest versions.
It is not exactly so. You may put the order to read and address to read in one cycle, and read data while puttin order to write, address and data to write in the following. It is simply that you may write while terminating the read.
I don't know. Or at least, I don't recognize the concept under those terms. But I am not native english speaver, it may just be a limited knowledeg of the language.
The PLB bus is treated as three buses, the address bus, the read data bus and the write data bus. The PLB spec allows all three buses to be performing separate transactions at the same time. This is what is meant by the term split-bus.
For example, starting from an idle state, a PLB master arbitrates for the address bus. Once granted the address bus, it sets up a transaction. Let us say it sets up a long burst write for this example. Once that transaction is acknowledged by a PLB slave, the PLB master releases the address bus, and starts putting data on the PLB write data bus. This is what is meant by decoupled address. The address bus is released as soon as the transaction is acknowledged, and can be used to set up more transactions.
A second PLB master can then request the address bus. Once granted, it can set up another data transaction. Let us say it sets up a long burst read. Once a slave acknowledges the transaction, the PLB master relinquishes the address bus, and the PLB slave starts putting data on the read data bus.
At this point in the example, there are two different data phase transactions going on at the same time, both a burst read, and a burst write.
The address bus is free at this point to be used to set up the next transactions. For example, another read can be started which will allow the targeted PLB slave to start fetching the data. As soon as the first PLB slave that was performing a read finishes its transaction of the data bus, the second one can start placing its data on the bus. This is what is referred to as address pipelining in the PLB spec.
If you have not already done so, download the IBM CoreConnect toolkit. It contains the specifications for the PLB, OPB, and DCR buses. It also has a simulation test bench with bus functional models and bus monitors.
There are a few differences between the IBM spec, and how Xilinx has implemented the CoreConnect buses in EDK. Make sure to read the Xilinx documentation carefully, and take note of the differences. I got to the IBM CoreConnect toolkit through the Xilinx web site, but it has been long enough ago that I don't remember the link.
Hi John, Many many thanks for you taking the time to explain this issue - It realy helps me alot. I read the PLB spec (from both xilinx/ibm) but couldnt find any good decription of those terms. So thanks again and have a nice weekend.
I have another question regarding the PLB-OPB, the PPC405 reference guide says that the PLB should be used for fast bus transactions and that the OPB is to be used for slower peripherals (GPIOs/UART etc.). My question is as follows - If I'm using a PLB-OPB bridge the data from/to the OPB will still go trough the PLB bus so how come it is says the the OPB usage takes some load of the PLB bus ? Thanks, Mordehay.
(address decoupling / pipeling) i.e. are there any specific powerpc command to tell the plb bus to operate this way or the other, or is it entirly up to the bus configuration and cannot be controlled in real-time ? Thanks, Mordehay.