PLB_EDK_Simulation

Hi , I am doing EDK Simulation of power pc(Ml 310)system,I have a master which does some write access to the external memory(plb bram), then in my application the processor is reading the same locations from the external bram (to which my dma master had written earlier).the first read happens from the processor ,after that it doesn't proceed further.(say instead some 8 reads ,only one read happens).Does any one came across this problem.Please help me out in this.Both the instruction and data resides in the plb_bram.

Regards, Mack.

Reply to
mmkumar
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I have seen this problem a few times. In both instances, the problem was caused by not giving the BRAM's enough time to "set-up" in the ModelSim simulation. Apparently, you have to wait more than 100 ns of simulation time for the BRAM's to be able to capture data you write to them, otherwise, you'll read back zeroes. This was even the case when the BRAM's were pre-initialized with instructions--I had to wait 100 ns to be able to read the instructions.

A caveat is defining a 100 ns in simulation because this depends on the timescale. In setting-up EDK, go to the "Project Options", select the "HDL and Simulation" tab and select "Verilog" in the HDL type to ensure that the simulation uses 1 ns for its timescale. Otherwise, in VHDL mode, I think it uses a 1 ps, so you have to use many more simulation cycles to set-up the BRAM's.

Reply to
Nju Njoroge

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