Hi , I am doing EDK Simulation of power pc(Ml 310)system,I have a master which does some write access to the external memory(plb bram), then in my application the processor is reading the same locations from the external bram (to which my dma master had written earlier).the first read happens from the processor ,after that it doesn't proceed further.(say instead some 8 reads ,only one read happens).Does any one came across this problem.Please help me out in this.Both the instruction and data resides in the plb_bram.
Regards, Mack.