PPC PLB <=> FPGA fabric

Hi all,

I want to load my PPC program in an external SRAM connected to the PLB bus on the PPC. But I fail to find any suitable IP with in EDK. For now I have bypassed the PPC and use a mux which either lets the PPC control the SRAM or the FPGA fabric. Since the program gets loaded at start up the PPC is hold in reset until the program is loaded.

However, I would like to have a general PLB master function which can access the PPC address space from the FPGA fabric. Does such an IP exist or am I missing something about EDK IPs which makes this possible?

Cheers, /Rick

Reply to
Rick North
Loading thread data ...

Knowing Xilinx, this is called "plb_ipif". Mind you, I haven't even looked, but if they had what you want, that's what they'd call it! I bet the "Create Peripheral" wizard (under the Hardware menu of XPS) will even connect it for you.

--
Ben Jackson AD7GD

http://www.ben.com/
Reply to
Ben Jackson

Checkout the documentation on opb_emc and plb_emc. Or just create a BSB design for a board that has SRAM and look at the design.

/Siva

Reply to
Siva Velusamy

I am in the same boat - i.e. I have the need to develop a master PLB interface for my own FPGA fabric logic. From what I have gathered so far, there is a PLB IPIF type component. However, I tend to agree with some on this NG who question how useful that really is - you still need to understand how the client side IPIF interface works, it takes up logic and will probably not be optimized for your application. At the end of the day, it may be better to just bite the bullet and read the PLB coreconnect spec and whip up your own interface with just the functionality you need.

What I am unclear on is what type of simulation models are available for helping me debug my own interface design. I just have Modelsim Xilinx Edition (not PE or EE). I haven't been able to get a clear picture of what is available for MXE. I have seen reference to bus functional models, but I think you need the outrageously expensive version of Modelsim to run it - can anybody verify whether this is true?

For your booting problem, could you allocate one or two block rams to hold a PPC bootloader? The bootloader could read your flash or wherever your code comes from using the DCR bus or something and initialize your external big RAM space that way.

-Jeff

Reply to
Jeff Cunningham

As an example of a simple PLB master you can look at the PLB TFT controller which ships as part of the reference designs for most of the Xilinx boards (for example

formatting link
It is a read-only master sitting on the PLB and fetching pixels from a framebuffer in main memory. The control interface is through DCR.

Building a master device for the PLB is in general simpler than building a slave device as the signaling is more straight-forward.

- Peter

Jeff Cunn> Rick North wrote:

Reply to
Peter Ryser

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.