Does Modelsim XE support coreconnect BFM simulation?

I am developing a EDK 8.2 component with a PLB master based DMA interface. It sure would be nice to use the coreconnect bus functional models such as PLB slave and PLB bus monitor to develop this core, but all I have for simulation is MXE. Does anyone know if this is possible? I downloaded and installed bfm_8_2.exe and can see source for all the BFM components; but the EDK "compile simulation library" command complains that I have MXE instead of PE/EE. I don't care about simulating other stuff in EDK, and normally I would simulate stand-alone but I get the feeling the BFM components are only meant for EDK. Had anyone here done anything like this?

Searching the xilinx database has not returned a straight answer.

Closest I can come is answer 19326 which refers to this:

(Xilinx Answer 16359) - 3.1/3.2 EDK - Does EDK support the ModelSim XE simulator?

but answer 16359 does not seem to exist.

thanks,

-Jeff

Reply to
Jeff Cunningham
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I used the bus functional models from the IBM CoreConnect toolkit with EDK 7.1. EDK generated all the scripts to compile and run the test bench for me, but I did not run ModelSim from within EDK. Having EDK generate the scripts was nice, but is something that you can do yourself.

The BFMs did not have any Swift models in them, so you do not need that feature. If I remember correctly, both VHDL and Verilog BFMs are provided, so as long as your code is all one or the other you do not need the mixed language feature.

Some of the files are large, over 50K lines I think, so if there is a line limit on the MXE version that might be a problem.

Regards,

John McCaskill

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Reply to
John McCaskill

Thanks, John. I was actually able to make this work in 8.2 as you describe. The "Generate simulation HDL files" command built the scripts and a starting point for a top level simulation file, then it was a matter of providing a clock and reset and fiddling with the BFL compiler. MXE is able to simulate it without complaining about any statement count exceeded, though it is not exactly fast. About 1 sec per microsecond for a setup with two 64 bit masters, one slave and a bus monitor (plus xilinx's PLB logic) on a 1.6 Ghz laptop.

-Jeff

Reply to
Jeff Cunningham

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