Hi, I am desging an master interface for 64-bit PLB.when i am not locking the bus and if i get a Mn_rearbitrate from the slave ,and am de-asserting and asserting the request after one clk.But it seems like the arbiter is not arbitrating the request from the me(master) after it got an M1_rearbitrate(never i get the bus , after that), how i can i proceed further to do my data transfer.

thanx, mack.

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I had designed a simple PLB master and posted some questions on the news group. The thread message was titled "Designing a simple PLB Master using EDK 6.3i". The last message in the thread was 2/1/2005. Read it is to see if it helps in general (refer to the PLB PDF document that I referenced in the thread).

Addressing your specific question, I have never dealt with the problem you are dealing with. Is the slave asking you to "retry" the request again?

All the best,

NN > Hi,

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Nju Njoroge

I have only tested my master pcore with a PLB BRAM in simulation and then in hardware (ML 310 with V2P30). I'm planning to migrate to using the PLB DDR (256 MB DDR mem that comes with the board). What kind of board/hardware are you using? Unfortunately, I do not have experience with the retry issue you are having. I imagine you re-issue the request, using the same parameters, but you have already tried that. Any one else with experience with this issue?

NN At 11:25 PM 2/17/2005 +0530, Kumar wrote: Hi , Thanks for replying, i really appreciate..yeah i will go thru the thread.. mean while i will probably explain u in detail....

I am desinging an master interface for PLB for EDK 6.3i (exactly for what u had done) and i tried edk simulation with BRAM, then my transaction went thru smoothly(ie no retry(rearbitrate) from slave).... but the moment i tried with SDRAM as my externl memory i get an Sl-rearbitrate from the slave and the PLB arbiter de-asserts the PLB_PAValid signal immedielty afetr seeing Sl_rearbitrate @ the pos edge of the clk.... then after that my master kept on requesting for the same address for which it didn't get an addr ack and got the retry(rearbitrate).... but the arbiter doesn't arbitrate at all after that(seems like).. and that PLB_PAValid signal is not going high at i cldn't proceed my transaction after that.....hope i am making sense to you...Please i would really appreciate if you could help me out in this.i am really stuck on this.......i tried all possiblities from the master side(like de-asseting and asserting the request again , nad later after some clock....but :-( no response from the arbiter.....)

Looking fwd for you answer...

thanx , Mack.

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Nju Njoroge




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Have you just tested the BRAM version in hardware? Try doing this first. After you get rid of the kinks for the PLB BRAM in hardware, then replace it with it with the PLB DDR version. *Theoretically*, you should be able exchange the pcores and it should work in hardware. Reading/Writing to the PLB DDR should be the same as PLB BRAM because the slave pcore controller is supposed to abstract away the memory type you are using. (Make sure the UCF file is set-up properly for the DDR--you can do this quickly with Base System Builder by creating a new project.)

Good luck, NN > Hi ,

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Nju Njoroge

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