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Xilinx EDK BRAM confusion

Hi all,

I have 2 questions on different ways of using BRAM in EDK:

  1. I have created a PPC system with DSOCM_BRAM and I am trying to make one side of it external for some external logic to access. The block is only 32 KB, but EDK would not allow me to set the address bus width (C_PORT_AWIDTH) to below 32 bit... This is confusing as according to the BRAM Block datasheet C_PORT_AWIDTH cannot be bigger than 17! So, should I just ignore extra pins or what?

  1. In the same system I have PLB_BRAM, which I want to be let's say 100 KB. However, the EDK seems to only accept a power of 2 size, i.e. either 64 KB or 128 KB. I was hoping that I could configure the controller for 128 KB range but physically assign a smaller block of memory to it. Is this possible?

Thanks, /Mikhail

Reply to
MM
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This is a document error. The bram_block takes in the address bus from the standardized bus (PLB, OPB, LMB, etc), and internally slices off the address lines. It's easy to recognize the usage from the HDL description. Take a look at /hdl/elaborate/_elaborate_v1_00_a/hdl/vhdl/_elaborate.vhd If you want to access one side externally, take a look at

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You'll have to accomplish this us> Hi all,

Reply to
Paulo Dutra

Reply to
Paulo Dutra

Thanks a lot Paulo!

/hdl/elaborate/_elaborate_v1_00_a/hdl/vhdl/_elaborate.vhd

Yeah, I actually found it myself, however I am still having some difficulties, which I am not sure at the moment whether they are related to BRAM. In any case I understand that the bus side is standardized, but why would the second side be similarly constrained ? BTW, I don't quite understand what happens to the second side by default? Is it simply hanging?

/Mikhail

Reply to
MM

Reply to
Paulo Dutra

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