Register file with LUTs in a SPARTAN3

You should get your HDL code to produce two dual-port primitives if you infer the register file with a single write and two reads. The total cost in the Spartan-3 is 4 LUTs (2 slices) per bit for up to 16 entries.

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I recommend you google for "register file fpga", for example see

If you can design your instruction set so the write port is always or usually one of the read ports, you might use a single bank of dual ported LUT RAM. That was one of the ideas behind the simpler gr0000 processors

Note in Spartan-3 only every other column of LUTs may be used as LUT RAM. :-(

Also, with Virtex-4's BlockRAM pipelined output registers, BlockRAM is finally becoming competitive with LUT RAM for register files (see also

There have also been some discussions on this the fpga-cpu mailing list. For example, start reading at

Jan Gray