Output pin load capacitance is used to roughly model the impact to timing and power that the load of downstream chips and your board trace have on the buffer. The reality is that the timing impact of a PCB trace depends a lot on its length relative to your edge rate. The most simplistic and pessimistic appraoch is to add the PCB trace capacitance and your far-end load caps and set this as your output pin load. If your I/O timing (such as Tco and Tpd) still meet your specs, you are probably ok.
In the absence of any information on your board and loadings, 10 pF is as good a guess as any, and 20 pF is likely pessimistic.
If you are using Quartus II v6.1 with Stratix II or II GX devices, or Quartus II v7.1 with Stratix III, you can enable "Advanced I/O Timing" under the TimeQuest settings. This feature of Quartus allows you to enter the parameters of the PCB -- near- and far-end loading, termination resistors, and PCB trace properties -- and Quartus will figure out the true impact that this has on your delay to both the near-end (FPGA pin) and far end (load). Quartus will also compute various signal integrity metrics (such as ringing) to see if you have any problems. See
for details on Advanced I/O Timing.
Or if you are very ambitious, you can run an IBIS or HSPICE simulation of your I/O. If you do, you will need to be careful how to combine the delay estimates from your tool with Quartus delays to avoid missing or double-counting delay -- see Application Note 424 --
Better yet, just get Quartus to write out the HSPICE netlist for your I/Os using the HSPICE Writer feature -- this will setup everything for you to avoid double- counting issues.
Paul Leventis Altera Corp.