Hello newsgroup users,
I have made a timing simulation for my SRAM-Controller and an external asynchronous SRAM.
I have used the FPGA Cyclone timing output file for my SRAM-Controller and the extra timing file for the SRAM model. Both components have been instantiated in a testbench.
How reliable are such simulations? Where do come problems along with that kind of simulations ? Is it recommendable to simulate that way when connecting some synchronous design with some asynchronous component?
I would appreciate your help or your field report about your timing simulation.
Thanks a lot.