I need to layout a Virtex 2 Pro board using a 672 BGA package. Does anyon have any tips for the placement of the bypass caps. I want to use 0603 cap and normal PTH vias. I can see that it might get a bit crowded trying t position a lot of caps under the device near to the power pins with al those vias.
The main principal behind decoupling caps is to minimize the area of the loop made by path from the power pin through the trace, cap and trace back to a ground pin. This area determines the inductance of the loop and limits the effectiveness of the capacitors. Anything that enlarges the loop area will create a problem with high speed decoupling.
My recommendation is to use even smaller caps, 0402 is good, and to put them right at the Vcc pins on the other side of the board, of course. If you check the impedance curves for ceramic chip caps you will find that at the frequencies of interest, they are inductive. So the actuall value of capacitace is not so important. The smaller package normally has lower inductance and therefore has a lower impedance regardless of capacitance. I checked these graphs a few years ago when
0402 was not so common and found that a 0.01 uF 0603 cap had a lower impedance than an 0805 0.1 uF cap.
So focus on lowering the impedance at the important frequencies, not necessarily on adding capacitance.
There are low inductance 0306 and 0508 capacitor packages that have the terminations on the broad sides rather than the narrow ends. Also putting the capacitor's power and ground vias beside the cap, as close to each other (and the cap) as possible helps cancel effective inductance (minimize loop area), especially compared to vias off each end of the cap. Using a pair of vias on both sides helps even more. Capacitors on the same side of the board should not share vias, but capacitors on opposite sides should (current flow directions cancel).
I'd say 0306 won't buy much in comparison to 0603 as the bonding wire lengths will be defining the loop inductance in both cases. At 1.27 mm pitched BGAs, I drill all pads and put the decouplng capacitors right on the bottom side pads (where power and GND are typically next to one another). The decoupling at higher speeds is done by the (power to GND) plane to plane capacitance, and of course by the on chip decoupling which must have been taken care of by the manucfacturer.
The best thing you can do for yourself is to use solid power and ground planes in your board and place them as close together as possible. A dielectric thickness between PCB layers of 0.004" (4 mils) is mainstream these days. As rickman stated, the goal is to minimize the loop area/inductance between the BGA balls and the bypass cap. Keeping the places close together is far more important in achieving this than placing the caps close to the balls, which is often impossible. There is a wealth of literature available on this subject if you look around for it.
Next, place the bypass caps for each voltage rail on the side of the board that is closest to the power/GND plane pair in your PCB stackup. Think loop area again. The vias from the cap to the planes form a loop, so the shorter the distance the better.
Third, there are good and bad ways to mount bypass caps. Andy mentioned this. Xilinx shows the good and bad mounting methods in XAPP623. I highly recommend you read this app note. Going back to loop area, keeping the two vias from the cap to the planes close together lowers the loop area. Using multiple vias lowers is even more, but I don't recommend this because it clogs routing and pokes even more holes in your already Swiss-cheesed power and ground planes.
Lastly, place the caps as close to the package as you can without destroying your routing channels. If you do everything above correctly then the distance from the BGA balls to the bypass caps is not that critical. Within a couple of inches is fine.
If you research this topic you'll also see varying recommendations on how to achieve a flat PDS (power distribution system) impedance over as wide a frequency range as possible by using several different cap values. This complicates the process a little but research shows it actually works. I still get away with using 0.01uF 0402 caps as my general bypass, with a few larger value (e.g., 2.2uF or 4.7uF) scattered around. Typically one larger value be I/O bank, one for VCCAUX, and maybe a couple for VCCINT.
Sort of like the first question, you can get a lot of different answers and they will all be correct. I find splitting planes is ok. But it is not easy to do well. The resistance of a sheet like a PCB plane can be expressed as "squares". For a given material and thickness, there will be a given amount of resistance per square area. It does not matter what the overall shape is, it can be broken into squares of any size and each one will have the same resistance. I've been told that a typical PCB will have about 1 mOhm per square. So don't make your power planes sections too long and narrow or the resistance will start to be significant.
In general, the power and ground plane coupling provides capacitance at the highest frequencies where caps are too high impedance to do much good. So don't skimp on the planes, keep them as large as possible. In the end you may need to add a second power layer or mix power and signals just because most parts require two voltages and running split power planes to the same part can be difficult.
But consider: while the capacitance is larger to have 100 sqare inches rather than 16, the point where the open edges of the PCB make the plane capacitance worthless due to replections (think quarter wave antenna here) is 2.5x worse. The bulk capacitance is better but the board capacitance will "open circuit" at a lower frequency.
As Howard Johnson pointed out in last week's Xilinx webcast, that point is rather moot for modern BGAs with the chips separated from the board by the "masking inductance" to where those higher frequencies are a problem for the BGA package or the chip itself.
Small power islands can be good as long as they have the appropriate decoupling to augment the power supply's response. Closer power/ground spacing means better capacitance - there are esoteric products that reduce the spacing to the 2 mil and under range but I don't know of any PCB houses that use it. Smaller planes are actually better if you have high frequency/current devices that have minimal impedance to the board when mounted where that "masking inductance" isn't an issue and the size of the board dictates where the distributed capacitance becomes less effective. Luckily we don't have many situations where that's a worry.
Resistance to the island is a concern. Capacitance on that island is a concern. One of the larger problems is when designers reference signals to those power islands and cross from island-to-island without significant decoupling island-to-island resulting in horrific crosstalk. If you want to reference signals to split planes, make sure they have a return current path that can *also* jump the plane split.
I sometimes add SMA connector footprints to my boards so I can TDR the bare boards and measure plane/pour noise on working boards. I've never been able to resolve an edge reflection, using a 20 GHz TDR. I think a typical pcb dielectric+copper structure is just too lossy. As far as I can measure, a small-gap ground/powerplane structure behaves like an ideal capacitor, and as you add bypasses *anywhere* on the board, it looks like a bigger ideal capacitor. I've seen no advantage to mixing ceramics, so I just use 0.33 uF.
Howard knows a lot of stuff, and makes up the rest.
That's hilareous, but partly true. I've been a Howie fan since Black Magic came out and it's been interesting to see what is gospel one year become anathema the next. The whole topic of high-speed design (SI, PDS design, modeling, etc.) reminds me of the FDA guidelines on what's good and bad to eat. It's all a constantly moving target, which is understandable because this is very complicated stuff.
After seeing some awful board stackups and PDS designs work flawlessly, I've concluded that a lot of the advanced art of PDS design is only needed for boards with super high-speed and high-current devices, like Pentium processors and the like. The research is driven mainly by companies like Sun, who deal in that area, and by the consultants and EDA tool vendors who have a vested interest in companies trying to follow the "state of the art" PDS design methodologies. Way overkill for most designs, even very large FPGA designs.
Signal integrity is a different story. There are tons of ways to get in trouble there, as I've proven to myself many times. :)
I've highlighted a number of howlers in Black Magic. Half his stuff is right and half is silly. If you know enough to tell the difference, you don't need the book.
His opinions on "return currents" are hilarious.
Exactly. Everybody has his religiously-observed way to do bypassing. The fact is that most any bypassing scheme works fine in most situations on multilayer/powerplane boards. I know a guy who uses no bypass caps at all, and that works too. I like four 0.33 uF caps per FPGA per supply, and that's just cowardly overkill.
I saw a board being stuffed once (on a Panasonic turret p-n-p, in a tin-roof assembly shack in Hamamatsu) that had over 3000 bypass caps, part of an Anritsu memory tester, as I recall.
Amen. And it's not getting any easier. The FPGA designers should take pity on us and give us the option to slow down i/o cells and clock buffers. Not every FPGA works flat-out.
You're right in that the decoupling at higher speeds is done by the planes (and on-package caps, if applicable), no the capacitors on the board. However, the on-board capacitors' job is to decouple the planes, not the device. Anything that can be done to reduce the effective inductance in the capacitor package and its connections to the planes (not just to the chip) helps, including broadside packages and adjacent/doubled vias.
We've had best luck when signal reference planes are continuous, whether they are power or ground. When we use segmented power planes (we don't segment ground planes anymore), we bury them between continuous ground or power planes, or at least try to keep the segmented layers away from signal layers. Differential signals, routed broadside, not over-under, are more forgiving WRT routing over segmented planes.
Don't keep us in suspense! Where are the funny parts in Howard Johnson's book?
Could you expand on this?
As far as I can tell, his opinion on return currents is that you have to be as careful about the return current as you are for the, uh, forward current. Is this incorrect? (or is it an incorrect characterization of his opinion?)
That is indeed his opinion, and it's goofy. He gives one example somewhere of a board with two ground planes, with a signal trace going from one surface layer to the opposite one through a via. He now suggests that the "return current" can't get from one ground plane to the other and gets confused or something. So he says to add *two* ground-ground vias, straddling the signal via, to let the return current find its way home.
Has anybody actually, ever, done anything this silly? The power and ground planes of a multilayer board are massively coupled by the dielectric capacitance. There's typically thousands of times more plane-plane capacitance than the C of an entire signal trace. The whole mess is equipotential as far as any tiny trace-capacitance currents can influence things. The trace doesn't care if it's "referenced to" its "original" ground, to another ground, to a power pour, whatever. It's all just one big AC ground.
HoJo also recently showed a picture of some spark gap corona that supposedly illustrated return currents, and Phil Hobbs pointed out (in s.e.d) that the sparks were in the wrong places. Phil and I were competing to lowball-bid to anybody willing to buy our copies of Black Magic.
I don't have simply the opinion that the return current has problems when switching layers, I know the return current has problems when switching layers. The distributed capacitance in 4-mil spaced power/ground plane combinations is only about 240 pF/in^2. While going from an outside layer to the inside layer involves a large percentage of the current staying on the 240 pF/in^2 power/ground plane pair near that signal, a switch from top layer to bottom layer involves the total switch of return current between outside reference planes at
*significantly* lower distributed capacitance. If there are no decoupling caps (for power/ground sitch) or ground-to-ground vias nearby (for ground/ground switch) there WILL BE crosstalk between nearby signals. This is basic transmission theory, no black magic.
The only silly thing is that the idea is dismissed so easily. I admit to having some trouble grasping the issue over a decade ago when I first had to worry about detailed, high speed board design but I got over my confusion.
What gets to be really amazing is when you're used to looking at signals on a scope and the rise/fall of a signal is very crisp but the logic level that follows is a regular mess; I say "regular" because I was "used to" seeing the signal all over the place when probing my wire wrap fixtures or poorly designed boards. Once a "good" board is brought to the scope, the "rock solid" behavior of the signals not only at the transition but in the logic levels before and after is impressive to the eye of one used to the flailing voltages.
Return currents switching between planes with no local route to make the switch DOES cause crosstalk and EMI. I have no doubt; I believe it's not a matter of "faith" but of physicas.