pcb layers on BGAs Spartan-3

Hi all, I am new in this forum, and I have not found a question as th stated below. Sorry if it has already done. I have been designin with Spartan-3 and as a consequence of the number of different powe suply and the pinout distribution on the board it is impossible to m to have a very reduced number of pcb layers. Allowing for simetrie between powers and gnd layers on the stack I almost can't decreas from ten. Is there any idea I am missing? maybe as 2.5 V is onl used in configuration I can create islands on the 3.3V layer an share the ground layer return between both power supply I think there must be something else that allow me to work effitienl wilt fewer layers Thanks in advanc

Reply to
calaf
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Without knowing what PCB technology you're using, it's impossible to say. Here are a few questions off the top of my head. Can you use microvias? What's your minimum track width? Minimum gap between tracks? What's the biggest BGA package on the board? Are you prepared to swap pins on the FPGA to aid the routing process? Is your volume enough to make it worth spending a lot of time on the layout? How fast are your risetimes and how long are your traces? Do you have Hyperlynx? Are you gonna insist on a plane for each of your power supplies, or do you know what you're doing? ;-)

256 pin BGA, 4mil tack/gap, uvias, two ground planes, routed powers, quick(ish) turnaround, long and fast traces = 6 layers, maybe even 4 with one ground plane if you're quite talented and have a lot of time. Cheers, Syms. p.s. Simetry (sic)? Pah, I spit on symmetry.
Reply to
Symon

Calaf,

See below,

Aust> Hi all, I am new in this forum, and I have not found a question as the

No. I am sure you have looked at it carefully, and the result is that the pcb's are definitely more complex for the newer technologies.

maybe as 2.5 V is only

Vccaux is used for the DCM, the IO predrivers, and the pass gate regulators (for interconnect). As such, noise on Vccaux will add to overall jitter. A dedicated plane for Vccaux may be too expensive, and not required. It may be shared with 2.5V IO Vcco banks, for example, but bypassing must be done well (see the SI web pages for pcb guidelines and bypassing guidelines on support.xilinx.com).

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Using more advanced bypass capacitors like X2Y style:

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or the other advanced caps:

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results in less area for the caps, and better bypassing overall, and may allow reduced plane area, as plane C from power to ground plane is effective above 100 MHz, where bypass capacitors are hardly able to do anything at all.

As mentioned above, there are techniques you can use, and tradeoffs you can make. Please work with your local Xilinx FAE, or Xilinx Disti FAE, as they have resources they can use to address the issue. In fact, my FPGA Lab supports the field in their endeavours, along with other groups within Xilinx to provide the best solutions.

Reply to
Austin Lesea

I have laid out my first board using the FT256. I have not had it fabricated yet. It is 4 layers 6/6mil track/space. The real killer was the size of the vias. I used 1 solid groundplane and planelets for VCCIO VCCAUX and VCCCORE. All IO voltages are the same which helps. I was not able to route out all the IO. I have posted a PDF file containing the PCB layers at

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Any comments on whether or not it will have decent signal integrity would be appreciated. Maybe it can provide some ideas.

Darrell Harmon

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Reply to
dlharmon

"dlharmon" schrieb im Newsbeitrag news: snipped-for-privacy@f14g2000cwb.googlegroups.com...

??? How is it possible to fanout the balls on just 2 signal layers (1 layer is "lost" for Ground, the other for VCC)? Or do you mean a 6 layer board (which leaves 4 layers for signals)?

Regards Falk

Reply to
Falk Brunner
[I have laid out my first board using the FT256. I have not had i fabricated yet. It is 4 layers 6/6mil track/space. The real kille wa the size of the vias. I used 1 solid groundplane and planelets fo VCCIO VCCAUX and VCCCORE. All IO voltages are the same which helps. was not able to route out all the IO. I have posted a PDF fil containing the PCB layers at
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An comments on whether or not it will have decent signal integrity woul be appreciated. Maybe it can provide some ideas.

As far I can gather I find some issues: There are some disposition o

vias on the 2.5V planelet that reduce significatively the path' width for currents (and therefore it raises the impedance. I hav found quite interesting the method used to take the 3.3V to the VCC pins but I wonder whether a trace (instead of a plane is not problem. Shouldn't a power plane be below or above all the pins o the FPGA as it happens with ground planes

Reply to
calaf

With 4mil track/space, it's possible to escape all but a few of the signals on the top layer only. And you can connect the IO you can't escape directly to VVCO or GND to improve SSO. You obviously don't escape all balls, only the signals. The power balls are connected thru via directly to the plane.

IIRC the "official" escape pattern for FT256 is 6/6 and uses top & botton layer only.

For the posted PDF, I find that the via restring is a little big and makes big hole in the powerplane. Most notably, the power distributed by the "annular" power plane looks like it's seriously cut at some place.

Sylvain

Reply to
Sylvain Munaut

"Sylvain Munaut" schrieb im Newsbeitrag news:42a9c242$0$329$ snipped-for-privacy@news.skynet.be...

Iam working on a design right now where we have to push a differential pair between 1mm pitch balls. **** pinout. But 4mil stuff isnt the thins you want. Expensive and not available from too many companys.

I doubt it. For a BGA fanout, you need n/2-1 signal layers, where n is the number of rows/columns (assuming you have a complete ball grid without space in the center. So for a 16x16 (FG256) you need 7 signal layers. To our advantage, the inner balls are just VCC/GND, so you get away with 4 signal layers.

Regards Falk

Reply to
Falk Brunner

"calaf" schrieb im Newsbeitrag news:jYGdnT7auunXIDTfRVn snipped-for-privacy@giganews.com...

This is the better solution (if you have the layer available) but split power planes are OK too. Just be carefull, dont use these as reference planes for high speed lines, this can bite you.

Regards Falk

Reply to
Falk Brunner

layer

Top layer takes front 2 rows of balls out without vias. The next two rows come out the bottom layer with vias. Both situations take 1 signal between ball or via.

Now - there are 4 signals left in the 5th row for the Spartan3 in the FT256 package - what about them?

By spreading the fanout from the center out, there's a cross where vias aren't populated. If one can fit two extra signals where the via would have been (easy) the inside 2 vias on the 5th row can route to the open channel and the 4th row vias for the center 2 rows fan out toward the center. The outside 2 vias on the 5th row fan out, changing the 4th row vias from inward fanout to outward fanout.

Looks clean. There's still room for another signal on the top layer in the middle where the fanouts spread away from the center.

The ASCII art will look clean only if viewed with a fixed-space font:

| | | | | | | | | | | | | | | | | | | | | O | O | O | O | |.| | O | O | O | O | \ \ | / / / \ \ \ \ | / O O | O O / . \ O O O | O .--' `--. / X O O' X . X `O O X

Reply to
John_H

pair

too

Are you sure? I thought this was industry standard now. It's a 'no added cost' feature from our pcb house.

space

Which is why you should use uvias. 4 mil track gap and microvias gets 8 balls deep out without a through via. The money you spend on uvias is easily recouped on layers saved. And your SI is much better. Great for diff pairs. Cheers, Syms.

Reply to
Symon

The vias are plated through. With metal. Like Khan, you're thinking too two dimensionally. Think like Mr. Spock.

No. That's why they invented bypass caps. Cheers, Syms.

Reply to
Symon

I did an S2E in the FG456 package in 8 layers, 6 mil design rules in places. The same arrangement would probably work for an S3 with three supplies if you split one of the power planes. The trick of course is to not go nuts with bypass caps.

I could post some layer pics to alt.binaries.schematics.electronic if there's demand.

John

Reply to
John Larkin

Why? They're all at AC ground.

John

Reply to
John Larkin

"John Larkin" schrieb im Newsbeitrag news: snipped-for-privacy@4ax.com...

Yes, but connected through vias + decoupling caps to "real" ground. It works, but less good than a real ground plane.

Regards Falk

Reply to
Falk Brunner

Take a look at

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For the FG256 they only show two signal layers.

Sylvain

Reply to
Sylvain Munaut

It isn't. I just used about 120 of the 171 IO. I used a solid ground plane and another plane for power. The first 2 rows were brought out on top and a few IO were brought out on the bottom.

Darrell Harmon

Reply to
dlharmon

Thanks for the tip. I took out a few vias and enlarged the 2.5V planelet. It is fairly solid now. Unfortunately the clearance around the via is the minimum allowed by the PCB maker (PCBTrain). The 3.3V IO does not really have a plane, but has an 0402 cap between the ground plane at each via. All of the IO are 3.3V LVCMOS. I am going to go ahead and build it. It has to be better than the alternative (PQ208).

Darrell Harmon

Reply to
dlharmon

two

Doh, I was looking at the wrong bit. Shouldn't've gone drinking on a school night yesterday! Syms.

Reply to
Symon

They're also connected by the parallel plane capacitance, which is typically pretty hefty when the dielectrics are properly thin. If you don't trust power planes for the "return current" you'll need a lot more ground planes, hence more layers. I do stuff with jitters in the low single digits of ps, and use microstrip traces referenced to power planes all the time.

I blame Johnson for all this obsession with "return currents."

John

Reply to
John Larkin

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