Virtex 4 package layout

Jon,

NC is just that: no connect. We reserve the right to do anything we might need to do with these pins, so just follow the rules: do not connect them to anything at all.

Austin

There was a time when you could rely on a label like that...when a door marked PRIVATE would be respected...when NC meant "NC"...when people didn't ask WHO SAYS I CAN'T PRESS THIS BUTTON??

But hey, it's 2008.

Mike

It depends on the interpretation of NC. (Beware of the hidden meaning of Aronyms) Some users mistakenly think it means: Xilinx has Not Connected anything to this pin, so I can connect anything I want to it. The more correct meaning is: Xilinx asks you Not to Connect anything to this pin, because it might already be used for mysterious undocumented purposes. This latter meaning goes back to vacuum tube (valve) sockets in the 'fourties. Peter Alfke

I'm aware of the ambiguity, but, when you use an abbreviation, it's your job to make sure the reader knows what it means. This is why, when I see AFAIK, HTH, IMHO etc, I think "another who wants to talk to the world but is too self-important to spend time writing in full".

At one time, semiconductor data sheets were superb documents, obviously written by professional technical writers. Now, it's clear that they're often written by engineers who believe that "anyone can write".

Mike

Austin, Peter, Are you sure? In UG075, the V4 packaging spec., Ch1 introduction it says:- "All of the devices supported in a particular package are pinout compatible and are listed in the same table (one table per package). Pins that are not available for the smaller devices are listed in the "No Connects" column of each table. " I think this means that you can connect up unused pins so that you can upgrade to a bigger part should the whim take you. Unless you have a different idea from me of 'compatible'? Cheers, Syms.

Symon,

OK, I will go quiz the "experts."

Not sure, but I do not think the "common large footprint" is a 'no-brainer' (common footprint fits all) for smaller parts (plugged onto a layout for a larger part) in V4.

Stand-by,

Austin

Austin,

Do you have any information?

Thanks

Jon

Just had a look at the ML405 board schematics and it seems to indicate tha the board can take an FX20, FX40 or FX60 device.

Jon,

OK, I was WRONG. I am not often WRONG, but, I can be WRONG, and I have been WRONG in the past.

NC is no connect. We don't use those pins, and they are not connected internally in V4, and V5.

Sorry for any confusion.

Austin

Ok thanks for clearing that up.

Jon

Jon,

No problem. I was initially too conservative as there was something I recalled in the back of my mind for V4.

That turned out to be not an issue.

Just wanted to be sure I didn't say anything that would lead to a bad pcb layout!

Austin

In my experience, NC means no internal connection. DNU means "do not use" or "make no external connection." There are many examples of this in JEDEC standard memories for instance.

I would like to add that Xilinx does a pretty good job of making the package footprint compatible across the parts that use it. This gets even better in the V5 series where the smaller parts just leave out entire banks instead of a spattering of pins within banks. This helps to maintain I/O functionality when going to a larger device. In the old devices, the additional I/O's separating the same pins of the package can cause excessive pin-to-pin timing when upgrading to a larger device. As one who works with board-level products, I've seen a number of headaches involved with making the FPGA size a customer option. With some vendors it was almost impossible to find a DDR memory pinout that works across the device range of a given package.

Regards, Gabor