PCB for FG456: layers

I believe you need six layers minimum. No need for buried vias as far I as know.

-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian

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0_0_0_0 snipped-for-privacy@pacbell.net where "0_0_0_0_" = "martineu"

with 6 perimeter I/O rows and GND, VCCINT, VCCO inside? Is it possible to design reliable board for it without buried vias? Any response will be appreciated.

You have posted an article to comp.arch.fpga via the Xilinx gateway to this news group. Unfortunately, this gateway mistakenly allows HTML posting, and even turns text postings into HTML. For all news groups, including comp.arch.fpga, the format is supposed to be text only. I have advised Xilinx about this problem, which they have said they will fix, but no schedule.

This concerns me for 2 reasons. First, many other users of comp.arch.fpga either can't read your postings, or it is a pain, and secondly, I maintain the archive of this news group at

and I have to spend several hours each month cleaning up the mess that is caused by HTML posts.

(11/08/2003

is currently off the air due to a Denial of Service attack. I expect that it will be enabled again early next month)

An alternative free system that will allow you to read and post articles to comp.arch.fpga and that does not have this problem is the gateway provided by Google, which also maintains archives (for all news groups) in text form only. (The archive for this news group at google should have the same content as the one I maintain, but mine has nicer indices and threading by author, topic, and date)

You can use google starting from the following page:

There is a link in the top right corner for posting. You may have to create an identity before posting, but that is free too.

Thanks

Philip Freidin

=================== Philip Freidin snipped-for-privacy@fliptronics.com Host for