Xilinx prom programming problem

I have a custom board with a V4 LX60 and a XCF32P config prom. I can config the FPGA directly via JTAG, but I cannot program the prom. I hope someone can point out the stupid mistake I'm making.

I am using ISE ver 8.1 and a parallel cable 4.

The two devices (fpga and prom) are in a single JTAG chain, with the prom first in the chain. Impact finds the chain and identifies both parts.I can tell Impact to by-pass the prom and load the .bit file to the FPGA; this works fine. However, if I tell Impact to generate a .mcs file and try to download that to the prom (bypassing the fpga), it starts the process, gets to 1% on the progress bar, then stalls.The TCLK line briefly shows some activity, then sits low. Eventually Impact gives an error message that the operation timed out.

The prom does get partially programmed, and the data is correct up to the point it just stops (remaining bytes are 0xFF). The correct portion varies, three trials yielded 5K, 15K and 53K bytes of correct data.

The JTAG connector is 1.5 inch from the prom. Readback from prom yields consistent results, and transferring .bit file to FPGA works, so I believe the hardware is good.

Does anyone have a suggestion as to what is broke? Thanks.


Reply to
sam catalpatechnology com
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sam catalpatechnology com schrieb:

If not a software bug ist looks like a partially broken PROM.

Regards Falk

Reply to
Falk Brunner

The only obvious problem is if you don't select "erase before programming". However this "PROM" is really a flash device and is likely to have a bad block.

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