Configuring FPGA using PROM/uP

There are application notes that talk about this. Go to support.xilinx.com and choose the Documentation link and then App notes (that's from memory--hopefully its right).

The key word that Xilinx uses for this is configuration. Once you figure that out its not hard to find the info you are looking for.

There is sample code available for this sort of thing although you will more than likely have to port it to your situation.

H> I must say that I find the xilinx docs to be vague.

have

If you want to control the loading process from the uProcessor and not the FPGA, you should use slave serial mode instead. In master serial mode, the FPGA drives the CCLK line out and expects one bit from the configuration bitstream on each rising clock edge. The CCLK will continue to switch until the configuration is complete. Since the minimum CCLK frequency in this mode is about 2.5 MHz, the uProcessor would need to respond very quickly to supply data a bit at a time. In slave serial mode, the uProcessor would drive CCLK and DIN, making sure that DIN is stable at the rising edge of CCLK. When the bitstream is completely shifted out, the uProcessor would wait for the done line to go high while continuing to shift 1's and toggling CCLK. This allows for the startup pipe to complete (see configuration options in bitgen).

To prepare a bitstream for loading, use impact to generate a HEX format file. These files have no relation to any particular PROM and contain only the bitstream stored as 2 hex characters per byte. I forget which bit to shift out first, but I think you want to shift LSB first if you generate the HEX file with the default option of "swap bits". If I'm wrong, instead of fixing your program, just un-check the "swap-bits" option and re-generate the HEX file.

I generally convert the HEX file to straight binary with a simple C program before storing it in the uProcessor's ROM.

You only need a Xilinx PROM if you want to directly program the FPGA without help from the uProcessor. In this case you would want to use master serial mode.

There used to be a .rbt file format - raw bits. The bits in the file were ascii 1s and 0s. That's horribly inefficient, but you don't have to worry about LSB vs MSB. And efficienty isn't too important if you are running it through a program only once to convert it to a format that's reasonable for your usage.

You can also use it just for debugging - look at the .rbt version to figure out how to parse the .hex version.

In master mode, YES, the FPGA has a complete sequencer to clock bits out of a serial PROM, deblock it, CRC check it, load it into the logic array, and finally terminate the process with a DONE signal if it completed the configuration correctly.

As long as it responds correctly to the INIT/ and serial clock signals, producing the correct bit on the first clock pulse, etc. then anyone's SPROM will work. There are several standards for the control of serial PROMS, so not all of them are compatible. The PROM has to be voltage compatible with the FPGA, as well.

Jon

signals,

work.

all

as

The bit order is important, the starting bit is not so important. The Xilinx devices look for a message header sequence, usually preceded in the bitstream by a bunch of 1's, to locate the beginning of the actual configuration data. Don't worry too much about missing or adding one or two bits in the beginning of the loading process.

You may also compress the image. I've used gzip for this in the past. The uP will have to decompress the image as it programs the FPGA.

This will increase the time taken to configure, but the space savings may be worthwhile.

Regards, Allan

that the uP simulates the JTAG ports to configure the FPGA. Also I am checked the XAPP502, where it discusses the slave serial and select MAP method of configuring.

Do the above methods require the use of Xilinx Cables or parallel cables?

I am guessing there is no size limit on the Flash PROM which I can use for the FPGA?

I would like to be able to use the microprocessor to do the whole conguration process.

Thanks

is

MAP

I'm assuming that the uP is on the same board as the FPGA, in which case you don't need Xilinx cables. However you may need some other connection to program the uP's flash.

use

No maximum limit, you need enough bits for the bitstream. Look at the datasheet for PlatformFlash (XCFxx) for representative bitstream sizes of various FPGA's.

Do you need to configure more than just the FPGA? If you want to do multiple chips in a JTAG chain you can do this, but for just an FPGA it is much easier to use slave serial mode. The uP flow for this is:

1. assert FPGA PROG# pin low.
2. wait for minimum reset time then de-assert PROG# high.
3. wait for INIT# to go high (you need a pullup on this pin).
4. place first bit of bitstream on DIN.
5. pulse CCLK high then low.
6. repeat 4, 5 for remaining bits of bitstream. While doing this monitor the INIT# line. If it goes low, the FPGA has detected a bitstream error.
7. place 1 on DIN.
8. pulse CCLK high then low until DONE goes high (pullup required).

If you *want* to use the Xilinx PlatformFlash for configuration, you will need to program the flash by way of the JTAG pins. This can be done by the uP with some help from impact for generating the required commands. In this case the FPGA would be in master serial mode and load automatically from the PlatformFlash at power-on or when the JTAG code to reset the FPGA (using CF output) is sent by the uP or other programmer. In this configuration you *could* use a Xilinx parallel cable to program the flash as long as the uP doesn't try to drive the JTAG lines while the cable is attached.