Hello,
I am trying to debug a scenario where I am unable to upload the FPGA image from the prom to the FPGA. The image downloaded to the prom sees correct.
iMPACT : 8.1.03i, Prom xcf32p, and Xilinx V Pro 100.
Downloading the .mcs file via iMPACT always works. But if I bitbang the generated .xsvf file to the prom it some times does not work. Although the prom verifies okay (through iMPACT) and also the checkum of the various regions are also fine.
I am using region 0 only and with compression mode enabled (the image size without compression is about 102%.).
The FPGA is in slave mode and apparently the clock also seems fine. I have verified the clock both after power up(reset) and with LOAD FPGA option enabled. The Prom seems to be clocking okay (internally clocked) but apparently the data bits are all high (parallel mode).
Is there a way to dump the xcf32p status registers?
Any suggestions would be helpful.
Thanks in advance,
-Kalpesh