Dear sir,
I have been troubled by this bug for past couple of hours. When i sythesize my verilog code it says: warning no Port FPGA51 has no net attached to it - no pad cells inserted at this port.
Port FPGA51 is where my serial data output from ADC is connected.
In my main module i have declared FPGA51 as an input. in the same module i also write: //DOUT isn't a direct input //FPGA51 is DOUT, wire DOUT to this pin input FPGA51; wire DOUT; assign DOUT = FPGA51;
DOUT is passed as an input into module instantiation, and in that module it is utilized after being synchronized with BCK.
Adc_Data_Manager data1(Reset, data_read_flag, DOUT, FSYNC, LRCK, BCK, VOC_DATA_MOD, AMB_DATA_MOD, data_ready_mod);
Adc_Data_Manager module declaration is as follow: module Adc_Data_Manager(Reset1, data_rd_flag, DOUT1, FSYNC1, LRCK1, BCK1, //input signals VOC_Result, AMB_Result, data_ready); //output signals
input DOUT1; input FSYNC1; input LRCK1; input BCK1; input data_rd_flag;
input Reset1;
output data_ready; output [8:0] VOC_Result; output [8:0] AMB_Result;
wire [8:0]VOC_SQD; wire [8:0]AMB_SQD;
wire sync_DOUT; wire sync_FSYNC; wire sync_LRCK;
//Synchronizing FSYNC, LRCK, DOUT with respect to BCK synch s1(BCK1, Reset1, DOUT1, sync_DOUT); synch s2(BCK1, Reset1, FSYNC1, sync_FSYNC); synch s3(BCK1, Reset1, LRCK1, sync_LRCK);
and the later in the code i am utilizing sync_DOUT when i start shifting data into my voice register with statements like these. VOC_DATA