"div_16M.v" generates a count that enables both "cnt_10.v" and subsequently "cnt_10_tens.v" when its(div_16M.v) count reaches all 1s.
To do the pause/start/stop function, I moved the "clr" function out of the two counter modules and into a module "cnt_pause.v" to enable/disable the master counter enabler "div_16M.v"...this makes the most sense(I thought)
Initially, "clr" was used to reset the counter to zero...this was tied to the DIP switch on the PCB.(this code is commented out)
This is my last shot at what I thought was "trivial"...I have changed it around a lot, but settled on this approach...I feel it is close, but I have begun to think otherwise...Please excuse the messiness and somewhat disarray.
// module: counter.v
// This is the top level module that ties all sub-modules together
module counter(clk,reset,lcd_com,one_dp,ten_dp,one_out,ten_out); input clk; input reset; output lcd_com; output one_dp; output ten_dp; output [6:0] one_out; output [6:0] ten_out;
wire nreset; wire pause; wire lcd_clk; wire tc; wire ce_tens; wire [23:0] ce_1s; wire [3:0] cnt_1s; wire [3:0] cnt_10s; wire [6:0] lcd1_out; wire [6:0] lcd10_out;
cnt_pause PAUSE( .clk(clk), .clr(nreset), .start_stop(pause) );
div_500K DIV_500K( .clk(clk), .clk_60(lcd_clk) );
div_16M DIV_16M( .clk(clk), .start_stop(pause), .enable(ce_1s) );
cnt_10 ONES( .clk(clk), //.clr(nreset), .enable(ce_1s), .tc(tc), .qout(cnt_1s) );
cnt_10_tens TENS( .clk(clk), //.clr(nreset), .ce_tens(ce_tens), .qout_tens(cnt_10s) );
hex2lcd ONES_LCD( .hex(cnt_1s), .lcd(lcd1_out) );
hex2lcd TENS_LCD( .hex(cnt_10s), .lcd(lcd10_out) );
lcd_mux ONES_MUX( .clk(clk), .cnt(lcd_clk), .data_in(lcd1_out), .lcd_seg(one_out), .lcd_com(lcd_com), .lcd_dp(one_dp) );
lcd_mux TENS_MUX( .clk(clk), .cnt(lcd_clk), .data_in(lcd10_out), .lcd_seg(ten_out), .lcd_com(), .lcd_dp(ten_dp) );
assign nreset = ~reset; assign ce_tens = tc & (ce_1s == 24'hFFFFFF);
endmodule
// module: cnt_pause.v
// This module ties the DIP switch function to counter enable.Pauses the //counter. // Continues counting toggled by user DIP and at last count value.
module cnt_pause(clk,clr,start_stop); input clk; input clr; output start_stop;
reg pause = 0;
always @ (posedge clk) begin if (clr) pause